we are using the HPS-DMAC (PL330) on a De0-Nano-SoC board to write and read data from the FPGA through a kernel module using the dmaengine API. Writing works fine (albeit pretty slow), but everytime we try to read data from the FPGA, a timeout occurs. The kernel module ist largely based on the fpga-dma driver provided by altera. I can see that the read transfer is arriving at my module in the FPGA (which is just a loopback FIFO), but for some reason the DMA callback function is never called and so a timeout occurs.
When I remove the timeout from the kernel module, the first transfer still arrives in the FPGA and reads some data. All following read-request dont reach the FPGA until I call a write to the FPGA. When executing the write, the read callback is called and the next read begins. This is very weird to me, I don't understand how the write call can call both the read and write callbacks.
My question is: what determines the end of a read access for the DMAC? Do I have to implement some additional signal in the avalon bus?
I hope someone can give us a hint! If you need any more information or code samples, please let me know!
Thanks in advance!