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Thread: Data transfer using buffer with (HPS--bridge--FPGA)

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    Default Data transfer using buffer with (HPS--bridge--FPGA)

    I have the DEO nano SOC and it looks like the Ethernet module is connected directly to the HPS. I can read/write data through the ethernet port... (PC--Ethernet--HPS) using c code. It looks like any data entering the rj45 cable goes through the HPS. The HPS has a fifo buffer system where I can "fread" an array from a file on a PC and get elements from the array as needed. I would like to do something similar with the FPGA component where I can input consecutive integers, use verilog or "block" style code to get data to my gpio ports.

    I am working on the following protocol:
    PC--Ethernet--HPS--bridge--FPGA--gpio.
    I have the first three working and I understand how to get the last two to work.
    Is there an example that allows one to set up the FPGA to read data stored in a fifo buffer where one can get and process it as needed? Is so, please direct me to that source. Thank you.

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    Default Re: Data transfer using buffer with (HPS--bridge--FPGA)

    Hello Doug,
    Can you please help me, i dont know where to start from PC--Ethernet--HPS. Please help me. Do you have any tutorials or codes ? Thank you.

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    Default Re: Data transfer using buffer with (HPS--bridge--FPGA)

    Quote Originally Posted by Doug314 View Post
    I have the DEO nano SOC and it looks like the Ethernet module is connected directly to the HPS. I can read/write data through the ethernet port... (PC--Ethernet--HPS) using c code. It looks like any data entering the rj45 cable goes through the HPS. The HPS has a fifo buffer system where I can "fread" an array from a file on a PC and get elements from the array as needed. I would like to do something similar with the FPGA component where I can input consecutive integers, use verilog or "block" style code to get data to my gpio ports.

    I am working on the following protocol:
    PC--Ethernet--HPS--bridge--FPGA--gpio.
    I have the first three working and I understand how to get the last two to work.
    Is there an example that allows one to set up the FPGA to read data stored in a fifo buffer where one can get and process it as needed? Is so, please direct me to that source. Thank you.

    Hi, were you able to find a solution to this problem? I am trying to implement similar thing as well but no luck till now.
    Thanks.

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