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Thread: Cyclone V SOC 256 bit F2S

  1. #1
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    Default Cyclone V SOC 256 bit F2S

    Hello,

    My design has a F2S_SDRAM bus between the FPGA to HPS.
    The current bus is set to 128 bits.

    I see however that it can be configured to be as wide as is 256 bits.

    Question:
    Is it "worth" it? I.E: will the 256 bit version have twice (or close to twice) the bandwidth compared to the 128 bit version ?

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    Default Re: Cyclone V SOC 256 bit F2S

    Did you try it? Did the performance increase?

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    Default Re: Cyclone V SOC 256 bit F2S

    No,
    I didn't try it.
    For 2 reasons:

    1. The 128 bit version (with burst lenght = 8) gives me more than enough bandwidth.
    2. The time domain that communicates with the F2S clocks @ 120MHz. If I double the width to 256 I'm almost certain that it won't meet timing.

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    Default Re: Cyclone V SOC 256 bit F2S

    I tried to use the F2S once but I could not do it. I used the F2H bridge instead.
    I was not using linux or other operating system, but baremetal.
    I saw some examples for the F2S using the baremetal but it was using some kind of an assembly file that was used for initializing the F2S bridge. Did you face something like this?

    My F2H clock was 100MHz. The transfer speed by using one DMA inside the FPGA was around 1 Giga Byte for reading from the DDR3 to the FPGA. F2H bit width of transfer was 128 bits.

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    Default Re: Cyclone V SOC 256 bit F2S

    Did you face something like this?
    Yes,
    I had to make a new pre-loader from the hand-off configuration files.
    It didn't work prior to this.

  6. #6
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    Default Re: Cyclone V SOC 256 bit F2S

    The main reason to use a 256-bit port is to get more bandwidth with less clock speed, or that you don't have two 128-bit masters in your system to merit two ports. Multiple ports is handy when you need to perform traffic shaping such as giving one port more priority than the other but if you are just looking for raw throughput a 256-bit port operating at 100MHz will use up all the memory bandwidth assuming you have an efficient master hooked up to it on the FPGA side of the device.

    You might find the Cyclone V SoC design here useful to see the effects of burst length has on the FPGA to HPS ports of the device: https://www.altera.com/support/suppo...n-example.html As you can see once you have a 256-bit F2S interface you don't really even need to use a bursting master because the traffic that goes off-chip gets downsized into SDRAM size bursts.

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    Default Re: Cyclone V SOC 256 bit F2S

    Hi BadOmen,
    I'm running a Linux OS with the bit file generated from a design modified from https://www.altera.com/support/suppo...n-example.html.
    I have a problem with the F2S interface. When I manually start a DMA transfer, I see the read request is asserted to the interface but no readdata/readdatavalid come back.
    Did I miss anything?
    Thank you so much!

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    Default Re: Cyclone V SOC 256 bit F2S

    I suspect the interface is not enabled yet. By default the F2S port should be held in reset internally until enabled. Are you using the HPS linux driver to configure the FPGA, I think enabling the F2S and bridges is something it does for you. In the example you referenced you'll probably find a section of code that enables the necessary FPGA interfaces if you want to see which registers those are.

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