# Thread: How to perform logical operation for two signal generated at diiferent clock cycle?

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## How to perform logical operation for two signal generated at diiferent clock cycle?

Hi everyone,
i have to random binary data signal,one starts at 100ns and ends at 1450ns ,another data signal starts from 14350ns and ends at 15000ns. I want perform xor operation of these two data signal in verilog.How to shift the signal or how to make the second data signal to start from 100ns so that both signal have data at the same at same clock cycle?.please help me....i'm new to this verilog code.

thank you.

2. ## Re: How to perform logical operation for two signal generated at diiferent clock cycl

Originally Posted by Meghana
Hi everyone,
i have to random binary data signal,one starts at 100ns and ends at 1450ns ,another data signal starts from 14350ns and ends at 15000ns. I want perform xor operation of these two data signal in verilog.How to shift the signal or how to make the second data signal to start from 100ns so that both signal have data at the same at same clock cycle?.please help me....i'm new to this verilog code.

thank you.
one way is to use two fifos, one dual clk on clk1/clk2, the other single on clk1. once both have data read out and xor.

Or use handshake approach instead of fifo but a shallow fifo is almost same cost as handshake.
Last edited by kaz; May 1st, 2017 at 07:07 AM.

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## Re: How to perform logical operation for two signal generated at diiferent clock cycl

can you please provide me the verilog code.. It will be very useful for me. i'm using microsemi Libero Soc 11.4v software to write verilog code.

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## Re: How to perform logical operation for two signal generated at diiferent clock cycl

can you please provide me the verilog code.. It will be very useful for me. i'm using microsemi Libero Soc 11.4v software to write verilog code.

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## unable to get postlayout simulation

I have a verilog code for memeory.I got the output for presynthesis,but postsynthesis i'm unable to get the simulation rersult

This is my actual code for memory...............
.................................................. ..........

`timescale 1ns/100ps

//<statements>

input sysclk;
input reset;

reg [7:0] count1_1,count2_1;
reg [7:0] count12_1,count11_1;
wire [7:0]count11,count12,count1,count2;

reg count1_en,count2_en,count11_en ,count12_en;

//////////////////////////////////////
//////////////DATA FOR MEMORY1
///////////////////////////////
// counter1

always @( posedge sysclk)
begin

if (reset==0)
begin
count11_en <= 1;
count11_1<= {8{1'b0}} ; end
else
if(count11_en == 1)
if(count11!= 8'd222)
count11_1<= count11_1 + 1;
if(count11_1== 8'd222)
begin
count11_en <= 0;
count11_1<=8'd0;
end

end
assign count11=count11_1;

always @( posedge sysclk)
begin

if(count11==0) begin
count12_en <= 1;
count12_1 <= {8{1'b0}} ; end
else
if(count12_en == 1)
if(count12_1!= 8'd222)

count12_1 <= count12_1 + 1;
if(count12_1==222)
begin
count12_en <= 0;
count12_1<=8'd0;
end

end
assign count12=count12_1;

//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test: memory1
//////////////////////////////////////////////////////////////////////
memory1 memory1_0(
.WD(count11),
.WEN(count11_en),
.REN( count12_en),
.WCLK(sysclk),
.RCLK(sysclk),

.RESET(reset)
);

.................................................. ................
.................................................. ...............
Warning: (vsim-3017) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Too few port connections. Expected 9, found 7.
#
# Region: /tb_mem/main_0/memory1_0
#
# Region: /tb_mem/main_0/memory1_0
# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count11_1' not found in the connected module (2nd connection).
#
# Region: /tb_mem/main_0/memory1_0
# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count12_1' not found in the connected module (3rd connection).
#
# Region: /tb_mem/main_0/memory1_0
# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count11_en' not found in the connected module (4th connection).
#
# Region: /tb_mem/main_0/memory1_0
# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'count12_en' not found in the connected module (5th connection).
#
# Region: /tb_mem/main_0/memory1_0
# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'sysclk_c' not found in the connected module (6th connection).
#
# Region: /tb_mem/main_0/memory1_0
# ** Error: (vsim-3063) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): Port 'reset_c_0' not found in the connected module (7th connection).
#
# Region: /tb_mem/main_0/memory1_0
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WD'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RD'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WEN'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'REN'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WADDR'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RADDR'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'WCLK'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RCLK'.
#
# ** Warning: (vsim-3722) C:/Users/Krishna/Desktop/monika/HARDWARETEST/RSTEST/synthesis/main.v(9290): [TFMPC] - Missing connection for port 'RESET'.
#
# Pausing macro execution
# MACRO ./run.do PAUSED at line 16
.................................................. ............................
.................................................. ..............................

the above mentioned error i got during postsynthesis simulation i'm not getting how to solve this error please help in this...........

i'm using libero Soc11.4v software to write and code and modelsim microsemi 10.3c simulator .

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## Re: How to perform logical operation for two signal generated at diiferent clock cycl

The binary data signal is 1 bit or multiple bits??

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## Re: How to perform logical operation for two signal generated at diiferent clock cycl

This code will give you an idea to implement.

// Design code
module Slave (clk,a,b,counter);
input clk;
input a;
input b;
input [31:0] counter;

reg [8:0] Y;
reg [8:0] storea=0;
reg [8:0] mem1;
reg [8:0] storeb=0;
reg [8:0] mem2;

always @(posedge clk) begin
storea <= {storea[7:0],a};
end

always @(posedge clk) begin
storeb <= {storeb[7:0],b};
end

always @(posedge clk) begin
if(counter == 'd11)
mem1 <= storea;
else if(counter == 'd21)
mem2 <= storeb;
end

always @(counter) begin
if(mem1!== 'dx && mem2 !== 'dx)
Y = mem1 & mem2;
else
Y = 'd0;
end

endmodule

//Testbench code
module TB;

reg clk=0;
reg a=0;
reg b=0;
int counter = 0;
Slave D1 (.clk(clk),.a(a),.b(b),.counter(counter));

always #1 clk = ~clk;

always @(posedge clk) begin
counter<= counter+1;
end

always @(counter) begin
if(counter >= 2 && counter <= 10)
a = \$random;
else if(counter >= 15 && counter <= 20)
b = \$random;
else begin
a = 0;b = 0;
end
end

/*always
#100 a = \$random;
#1450 a = 0;
end

initial begin
#14350 b = \$random;
#15000 b = 0;
end */

initial
#100 \$finish;

initial
begin
\$dumpfile("design.vcd");
\$dumpvars;
end

endmodule

Thanks

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