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Thread: ALTLVDS Failing timing on simple interface

  1. #1
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    Default ALTLVDS Failing timing on simple interface

    Hi
    I am failing timing implementing a simple ALTLVDS The clock speed is 200MHz the de-serialization factor is 2.
    I am interfacing a CYCLONE V SOC system to a two channel, 14 bit ADC (ADS4249) ADC via LVDS I have 14 LVDS lanes in total to cover both ADC channels. Each lane does two bits.
    My problem is that Timequest is failing on setup time.

    I have not specified any constraints in my Timequest sdc for the LVDS.
    I am using Quartus 14.1. I notice that the megawizard greys out nearly all the options as soon as I select a deserialization factor of 2. Is this because ALTLVDS does not use PLLs for de-serialisation factors of 2?

    Please can anyone help me get my design through timing?
    Thanks
    Dave

  2. #2
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    Default Re: ALTLVDS Failing timing on simple interface

    Hi,

    Why are you using ALTLVDS IP? In my opinion this IP is not suitable for your needs. If I were you a would use simple DDR input registers with PLL.

  3. #3
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    Default Re: ALTLVDS Failing timing on simple interface

    Quote Originally Posted by vlrean View Post
    Hi,

    Why are you using ALTLVDS IP? In my opinion this IP is not suitable for your needs. If I were you a would use simple DDR input registers with PLL.

    Hi Thanks. I think you make complete sense. I will try ddrio. Cheers Dave

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