Results 1 to 5 of 5

Thread: Qsys-generated .SDC files for HPS generate zillions of warning messages

  1. #1
    Join Date
    Jun 2017
    Posts
    3
    Rep Power
    1

    Default Qsys-generated .SDC files for HPS generate zillions of warning messages

    I have a Qsys design named "soc_system" which instantiates the HPS. This is a Cyclone V SOC, running Quartus Prime 17.0.

    When generating HDL, Qsys seems to be outputting two SDC files: soc_system_hps_fpga_interfaces.sdc and soc_system_hps_hps_io_border.sdc. Both these files seem to be automatically included in the project under soc_system.qip. Both of these files generate compile warnings on every single line, thereby resulting in hundreds and hundreds (and hundreds more) spurious warning messages completely clogging my compile reports. Examples:

    On soc_system_hps_hps_io_border.sdc, the first warnings look like this:
    Warning (332174): Ignored filter at soc_system_hps_hps_io_border.sdc(1): hps_io_hps_io_emac1_inst_TX_CLK could not be matched with a port
    Warning (332049): Ignored set_false_path at soc_system_hps_hps_io_border.sdc(1): Argument <to> is an empty collection
    Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]


    The rest are similar. The reason is that my top-level ports are not named that way. Those names reflect the names of the ports to the soc_system.v module.

    On soc_system_hps_fpga_interfaces.sdc, the first warnings looks like this:
    Warning (332174): Ignored filter at soc_system_hps_fpga_interfaces.sdc(3): *fpga_interfaces|f2sdram~FF_3768 could not be matched with a register
    Warning (332049): Ignored set_false_path at soc_system_hps_fpga_interfaces.sdc(3): Argument <from> is an empty collection
    Info (332050): set_false_path -from [get_registers {*fpga_interfaces|f2sdram~FF_3768}]

    Here I have less insight into the nature of the problem.


    I am not clear if this is normal, or if it's an indication that there's something wrong in my design or on my project configuration, or what I can do about it. Anyone have any insight?

  2. #2
    Join Date
    Jun 2017
    Posts
    3
    Rep Power
    1

    Default Re: Qsys-generated .SDC files for HPS generate zillions of warning messages

    Hmm, I just looked and saw that they are specifically included in the Timequest settings. Maybe I should just remove them? But I'd like to understand them better before I start trying stuff at random.

  3. #3
    Join Date
    Oct 2017
    Posts
    15
    Rep Power
    1

    Default Re: Qsys-generated .SDC files for HPS generate zillions of warning messages

    I am not that familiar with this topic, however yesterday I read that if .sdc files are part of the .qip "library", they should not be included in the TimeQuest settings as well. See the Quartus Handbook vol 3 https://www.altera.com/content/dam/a...qts_qii5v3.pdf page 7-57 or page 106 ("If SDC files for IP blocks in your design are included through with a .qip, do not re-add them manually.")

  4. #4
    Join Date
    May 2013
    Posts
    725
    Rep Power
    1

    Default Re: Qsys-generated .SDC files for HPS generate zillions of warning messages

    Something is messed up with your HPS peripheral I/O settings. Go back to the HPS parameter editor in Qsys and check the I/O sets you are using for the particular peripherals you want to use. Look and see if you see any warnings in the parameter editor that might help figure this out.

    Also, have you made I/O connections in the Pin Planner? You say you are not using those names, but then what are you naming everything? Are you assigning other signals in the design to I/O pins reserved for the HPS?

  5. #5
    Join Date
    Jun 2017
    Posts
    3
    Rep Power
    1

    Default Re: Qsys-generated .SDC files for HPS generate zillions of warning messages

    Quote Originally Posted by sstrell View Post
    Something is messed up with your HPS peripheral I/O settings. Go back to the HPS parameter editor in Qsys and check the I/O sets you are using for the particular peripherals you want to use. Look and see if you see any warnings in the parameter editor that might help figure this out.

    Also, have you made I/O connections in the Pin Planner? You say you are not using those names, but then what are you naming everything? Are you assigning other signals in the design to I/O pins reserved for the HPS?
    For soc_system_hps_hps_io_border.sdc, the problems seems to be that I didn't name my pins the way Qsys expected me to. So it generated, for instance,
    set_false_path -from * -to [get_ports hps_io_hps_io_inst_emac1_TXD0]

    Whereas I named that pin more rationally to hps_emac1_TXD0. My short term fix was to edit that SDC file after each Qsys generate, swapping "hps_io_hps_io" for simply "hps", and getting rid of "_inst_". That fixes it, since then the SDC file matches my pin names. The problem is that it's another step I need to take after running Qsys generate (even if it's scripted). There are other ways I could handle it too, all with varying pluses and minuses. Like, I could rename all my pins to match the ones Qsys expects. That would really be the solution, even if I'd have to live with all those hideous pin names. I'll probably give in and do that eventually.

    Since the interior workings of the HPS are rather opaque from a Qsys standpoint, I don't believe there's any straightforward way to change the names of the various interfaces it uses when exporting its I/O. So I'm pretty much left with taking what it gives and making the best of it.


    Soc_system_hps_fpga_interfaces.sdc remains a mystery. The comment at the top of the file says
    # These false paths fix a problem with the HPS timing library for the F2SDRAM bridge.
    # This issue only affects timing analysis. There are no functionality problems with the bridge

    Sounds fine, but none of the set_false_path assignments ever match anything in my design. For a while I was just commenting out all the lines in the file until I realized that I could more easily nuke all the warnings withe message suppression manager, using the file name as keyword. Solved.

Similar Threads

  1. I got this warning messages. Is is OK?
    By zeroful1 in forum Quartus II and EDA Tools Discussion
    Replies: 1
    Last Post: September 12th, 2016, 10:16 PM
  2. Help:Unable to generate Qsys synthesis files after version upgrade
    By neling in forum General Altera Discussion
    Replies: 0
    Last Post: February 12th, 2014, 12:12 AM
  3. Warning Messages in conjunction with for PLLs
    By cchabrie in forum Quartus II and EDA Tools Discussion
    Replies: 7
    Last Post: June 23rd, 2010, 11:29 AM
  4. Warning Messages Max+ Plus Advanced Synthesis
    By jsanco in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 2
    Last Post: March 29th, 2010, 06:00 AM
  5. SDC constraint warning messages during synthesis
    By KxAlpha in forum Quartus II and EDA Tools Discussion
    Replies: 0
    Last Post: January 22nd, 2010, 05:52 AM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •