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Thread: FPGA freeze while using remote update IP - Cyclone V

  1. #1
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    Default FPGA freeze while using remote update IP - Cyclone V

    Hi,

    I am using a cylcone V along with EPCQ128 flash memory. The design incorporates a remote update block to switch between factory and application image.

    POF checking is on and I have signals running from remote update block and the ASMI interface via multiplexer (I'm using the ASMI block to write and read from the flash).
    I have the factory configuration starting from address 0x000000. I have double checked the settings, and the configuration mode is active serial X 1, remote.
    Watchdog is enabled and the timeout value is set to 4 seconds - 0x149.
    The state machine is exactly same as what is in the reference design for remote update.

    Application image starts at address 0x400000 - sector boundary. Both factory and application bitstreams are compressed (Factory image ends way before address 0x400000; No overlap)
    Using the ASMI interface, I double checked the presence of application configuration by comparing the read data with the .rpd file.

    During power-up, I see the factory configuration. I see all the signals and states on signal tap - So far so good.
    I provide the ANF start strobe, which in-turn provides the reconfigure strobe, and I see that there is no POF error (Which I believe indicates that the core located the application image), but the FPGA freezes. The application image is not loaded.
    Initially, the logic inside application image did not have the remote IP instantiated. I then experimented by instantiating the core, and resetting the reset_timer pin by providing a high to low signal (high for 250ns as per the data sheet). I still see the same result as mentioned above.

    One thing worth noticing was the nSTATUS pin. I was under the impression that the nSTATUS pin goes low when there is an error during configuration. What I see is a periodic signal. Attached the waveform snapshot. I don't know if anything can be made out of this.
    nSTATUS and nCONFIG pin are pulled up to 3.3V via 10k resistors.

    Any help regarding this issue would be really appreciated.


    Thanks,
    Kamath
    Attached Images Attached Images

  2. #2
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    Default Re: FPGA freeze while using remote update IP - Cyclone V

    Update -

    I did some digging, and finally got the block to work.

    I've prepared a checklist to debug the core:

    1. Make sure the design which has the factory configuration is in remote mode. Choose the correct configuration method (ASX1, ASX2).
    2. Check configuration pins on the board -- nSTATUS, nCONFIG, config_done - See that the pins are pulled high/low. Check for voltage and resistor values on the device handbook.
    3. Check MSEL pins on the board - Depending on the configuration scheme you use, pull it high/low with appropriate resistor values - check the device handbook for more details.
    If either of these are not set correctly, the remote update block WON'T work.


    This would be a nice debug strategy to follow, if the IP fails in spite of all the above mentioned things are OK.
    1. Most of the reference designs don't have POF checking ON. Use POF checking and mux the pins with the ASMI address, dataout and data valid signals.
    Debug: Use signal tap or any other method to probe POF error signal. If the signal is high, the application configuration is not written to the flash at the desired address.

    2. If watchdog is enabled, you will have to PERIODICALLY reset it in the application image.
    Debug: Disable the watchdog and see if the application image is up. If yes, enable the watchdog in the factory image. In the application image, you will have to reset the timer periodically.
    The frequency at which the timer is reset must be greater than the frequency at which the watchdog times out. This should get the IP working.


    Hope this helps.
    Kamath

  3. #3
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    Default Re: FPGA freeze while using remote update IP - Cyclone V

    Thanks Vittal, that got it working!

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