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Thread: Need help capturing the period of a wave form. (Verilog)

  1. #1
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    Default Need help capturing the period of a wave form. (Verilog)

    My code requires that I store the value of an input signal's period in a register. I have mocked up the code below to register the period, but I cant yet confirm that it works. In your experience do you see anything that is immediately wrong with it. I am trying to learn how to use modelsim at the moment please forgive me. Sys_clk is a 50MHz clock, and the in_signal I am working with right now is 2Hz but that may change.
    Desired Inputs: System Clock, RST from controller, a signal of unknown frequency and duty cycle that is less than 50MHz(the freq is constant).
    Desired Output: A registered period value in decimal form

    <!-- language: verilog -->module t_sampler(input wire in_signal, input sys_clk, output reg [31:0] total_T);reg [31:0] pos_length;reg [31:0] neg_length;reg pos_cntstop;reg neg_cntstop;always @(posesge sys_clk)beginif(in_signal)begin pos_length <= pos_length +1;endelsebegin pos_length <= pos_length; pos_cntstop <=1;endif(!in_signal)begin neg_length <= neg_length +1;endelsebegin neg_length <= neg_length; neg_cntstop <=1;endif(neg_cntstop && pos_cntstop)begin total_T <= neg_length + pos_length; neg_cntstop <=0; neg_length <=0; pos_cntstop <=0; pos_length <=0;endendendmodule

  2. #2
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    Default Re: Need help capturing the period of a wave form. (Verilog)

    Can you add some carriage returns here? This is pretty much unreadable. Though I do see that posedge is spelled wrong.

  3. #3
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    Default Re: Need help capturing the period of a wave form. (Verilog)

    When attaching code fragments to posts use the advanced editor and put the "code" tags around it. Otherwise all your line breaks will be lost like what happened in your original post.

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