Results 1 to 4 of 4

Thread: Is there a best practise to build a Clock Synchronizer for a Cyclone IV or V?

  1. #1
    Join Date
    Jul 2012
    Posts
    4
    Rep Power
    1

    Default Is there a best practise to build a Clock Synchronizer for a Cyclone IV or V?

    I'm teaching techniques to cross clock domains (CDC), and I need to develop some demonstrators.

    For some techniques, you would cascade D-Type FlipFlops without any combinational logic between them. These D-Types also need to be as close as possible, and have the fastest setup time possible of course.

    We are using a Cyclone IV on a DE0-Nano board, but I assume the issue is the same for the DE1 boards (which we will move to next year)

    It's straightforward to write VHDL to build a clock synchroniser. The issues I am uncertain about is how to constrain the synthesis to minimise mtbf.

    Maybe there is a standard component that allows me to build a clock synchroniser? (I could not find one).

    Many thanks in advance.
    Last edited by noutram; August 9th, 2017 at 01:54 AM. Reason: Update on platform

  2. #2
    Join Date
    Oct 2008
    Location
    London
    Posts
    3,559
    Rep Power
    1

    Default Re: Is there a best practise to build a Clock Synchronizer for a Cyclone IV or V?

    Quote Originally Posted by noutram View Post
    I'm teaching techniques to cross clock domains (CDC), and I need to develop some demonstrators.

    For some techniques, you would cascade D-Type FlipFlops without any combinational logic between them. These D-Types also need to be as close as possible, and have the fastest setup time possible of course.

    We are using a Cyclone IV on a DE0-Nano board, but I assume the issue is the same for the DE1 boards (which we will move to next year)

    It's straightforward to write VHDL to build a clock synchroniser. The issues I am uncertain about is how to constrain the synthesis to minimise mtbf.

    Maybe there is a standard component that allows me to build a clock synchroniser? (I could not find one).

    Many thanks in advance.
    I wire two registers directly...and leave it to tool. The ideal is balanced setup/hold rather than best setup.
    You may therefore add max/min delay on that path to target balanced timing but I never done that.
    you also need false path at cross over.
    dual clock fifos sdc may give better details.

  3. #3
    Join Date
    May 2013
    Posts
    480
    Rep Power
    1

    Default Re: Is there a best practise to build a Clock Synchronizer for a Cyclone IV or V?

    Check out the Managing Metastability chapter in the Quartus Prime handbook:

    https://www.altera.com/products/desi...e/support.html

  4. #4
    Tricky is offline Moderator **Forum Master**
    Join Date
    Oct 2008
    Posts
    5,753
    Rep Power
    1

    Default Re: Is there a best practise to build a Clock Synchronizer for a Cyclone IV or V?

    Quote Originally Posted by kaz View Post
    I wire two registers directly...and leave it to tool. The ideal is balanced setup/hold rather than best setup.
    You may therefore add max/min delay on that path to target balanced timing but I never done that.
    you also need false path at cross over.
    dual clock fifos sdc may give better details.
    Altera Dual clock fifos had false paths across the clock domains embedded in the core until recently. I think there is now an idea that some people would rather put a max delay constrain across the path rather than a false path, as this would prevent the tool placing the false paths registers at opposite ends of the chip (though this is unlikely, its not beyond the realms of probability). The problem with the embedded constraint is that it cannot be overridden, as false path always takes priority.

    From the DC fifo user guide, https://www.altera.com/en_US/pdfs/li...ug/ug_fifo.pdf, P21, you can see this new option is from Q15.1+ and only applies to arria 10. If you have an older device, you're stuck with a false path.

Similar Threads

  1. Synchronizer chains not recognized
    By arne in forum Quartus II and EDA Tools Discussion
    Replies: 0
    Last Post: March 6th, 2017, 06:32 AM
  2. 2 FFs synchronizer constraint
    By galign in forum Quartus II and EDA Tools Discussion
    Replies: 3
    Last Post: March 18th, 2013, 06:18 AM
  3. PLL synchronizer
    By iozana in forum General Altera Discussion
    Replies: 1
    Last Post: February 28th, 2013, 02:42 AM
  4. VIP suite: control synchronizer
    By clivewmwalker in forum DSP Builder and DSP IPs
    Replies: 0
    Last Post: December 20th, 2012, 06:04 PM
  5. Do I need synchronizer block for this
    By cpugeek in forum Verilog and System Verilog
    Replies: 6
    Last Post: November 29th, 2012, 07:23 PM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •