Page 2 of 2 FirstFirst 12
Results 11 to 12 of 12

Thread: FPGA to SFP

  1. #11
    Join Date
    Apr 2013
    Rep Power

    Default Re: FPGA to SFP

    Quote Originally Posted by ak6dn View Post
    SFP modules are AC coupled (inline capacitors within the module) by design. Driving the SFP using two single ended outputs in a pseudo-differential mode can be made to work (especially at lower signal bandwidths like 100Mb ethernet or 155Mb OC3). Once you get to 622Mb OC12 or higher using this mode is not likely to work well.

    Receiving however is a different matter. Since the signals are AC coupled, at the SFP pins you will see single ended signal swings around 0V DC (like -1V to +1V). These levels are not within the valid input range for a single ended receiver, which will be 0V to some VCCIO like 3.3V/2.5V/1.8V. You must terminate the signals in the correct line impedance (ie, 40 to 80 ohms, depending on layout) to maintain signal quality, AND add a DC offset to move the signal into the switching range of the receiver.

    Typical boards that interface to SFP modules have resistive termination circuits that perform the termination/restore to (usually) 100ohm differential and a Vt that depends on the receiver, typically this is VCCIO-1.2V or so.

    So I think you need to rethink your board design. Just connecting an SFP module to single ended I/O on the FPGA with no external signal conditioning circuit will not work.


    Thanks for your reply.

    As per your guideline, i have designed breakout board for LVDS driver and signal conditioning.

    Here i need clarification in the design. This LVDS driver will be 100ohm impedance. I would like to know, whether both FPGA differential IO pin and SFP transceiver pins are 100ohm impedance or different impedance.

    I have attached schematic of the breakout.

    Please verify, whether it is ok or not.?
    Attached Files Attached Files

  2. #12
    Join Date
    Oct 2008
    Silicon Valley, USA
    Rep Power

    Default Re: FPGA to SFP

    Have you read the TI datasheet for this device? Specifically section 11.2.8 describes how to do AC coupled signal reception (which will be what you get from the SFP module output). Basically you need 50ohm pullups on both P/N to Vbb. Read the datasheet for all the details.

    The TX input into the SFP will be just direct wires, as the SFP module is internally AC coupled and has 100ohm differential termination across P/N.

    Note the 100ohm differential / 50ohm single-ended signal termination and routing means you adhere to those rules when designing the PCB trace layout, and implement the appropriate trace widths and spacing on your PCB to give you those trace impedances.

Similar Threads

  1. Replies: 22
    Last Post: April 13th, 2017, 09:42 AM
  2. Cylone2 - FPGA Not Detecting - Hardware Issue?. FPGA Device Failed?
    By manoj87 in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 7
    Last Post: May 7th, 2015, 08:05 AM
  3. Replies: 9
    Last Post: September 19th, 2014, 04:51 AM
  4. Replies: 0
    Last Post: January 23rd, 2014, 06:15 AM

Tags for this Thread


Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts