I've got an SOC design that im trying to simulate in cadence NCSim 15.20-s005, and when the reset to the h2f_lw_axi module is asserted, i get the error "testbench.dut.ufpga_core_inst.mm_interconnect _0.h ps_0_h2f_lw_axi_master_rd_limiter: Error: unexpected response: pending_response_count underflow", and then the AXI repeats the last few transactions that it did before the reset, often resulting in a failure for reset tests that want to check the effected registers after reset.

I've tried digging around probing signals within that module, but the problem hasn't revealed itself.
my task for executing an axi transaction was written using the mentor_vip_ae_usr.pdf guide, and is

Code:

task automatic fpga_reg_write; input [31:0] addressi; input [31:0] datai; begin `bfm.wait_on(AXI_CLOCK_POSEDGE); $display ("TSK: Register write, adddress %h, data %h, at time %t", addressi, datai, $time); write_TH = $sdi_transaction("", my_FH, "FPGAWriteType", "FPGARegWrite", "Write FPGA Register through AXI"); $sdi_set_attribute(write_TH, "Address", addressi); $sdi_set_attribute(write_TH, "Write Data", datai); trans = `bfm.create_write_transaction(addressi[20:0]); trans.set_data_words(datai, 0); trans.set_write_strobes(4'b0011, 0); `bfm.execute_transaction(trans); repeat (4) @(posedge clk_25 $sdi_end_transaction(write_TH); endendtask

am I doing anything wrong here to instigate this problem?


thanks