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Thread: AltLVDS_RX weird data patterns

  1. #1
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    Default AltLVDS_RX weird data patterns

    Hello,

    My problem is the following:

    I am using the ALTLVDS_RX megafunction on a Cyclone V, without DPA, but on the side of the FPGA where dedicated SERDES circuitry is supported(on the bottom). The input is 4-lane, 7-bit serial with 519.75 Mbps each, and with a clock of 74.25 MHz.

    I have manually adjusted the phase of the input clock for word alignment and tried for bit alignment, still, I am getting weird data. The problem is, the data wouldn't make sense even if I messed up the bit alignment.
    Examples: on the attached picture FF1, the pattern should be FF 00 00 AB, it is EF 10 00 A9; on the picture FF3, the pattern should be FF 00 00 9D. The weird thing is, that if the bit alignment was messed up, I would expect no mistakes in the middle of data words having the same value(1111111,0000000), but there are mistakes there.

    I have looked at both the user guide for the megafunction(https://www.altera.com/content/dam/a...ug_altlvds.pdf) and the design guidelines for implementing LVDS interfaces(https://www.altera.com/en_US/pdfs/li...e/an/an479.pdf). I have read both parts regarding timing closure and added the input delays for RSKM(I didn't know how to determine the real RCCS, so I just set the largest possible values fitting into timing), it didn't change anything.

    Does anybody have an idea how could these data patterns emerge or what could be wrong with my design?

    Best regards,
    Tibor
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    Last edited by rozsatib; August 11th, 2017 at 08:44 AM.

  2. #2
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    Default Re: AltLVDS_RX weird data patterns

    Apart from timing issues and as far as I know you, the designer, need extra logic to get word boundaries from parallel stream. i.e. you need to send a known data stream then align it until you get it back by searching through all possibilities and stop when you get the correct words

  3. #3
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    Default Re: AltLVDS_RX weird data patterns

    I have already done something like that. Originally, the phase difference between the clock and the data was set to 0 ps in the megafunction; then I began to increment it by the data rate duration. I stopped when all the data lines were in the correct position, and tried to fine tune it by finding the center of the data window by incrementing/decrementing the phase difference by small amounts. I didn't find a point where the data were all correct,though, just close to it.

    The data is set up so when deserialized, there are predetermined values to sync to(12 from the 28 values). But because the sync signals are incorporated in the data, I deemed it was enough to set the phase shift manually in the verilog file of the megafunction(the megafunction wizard has weird values for phases, some cannot even be applied), because the relationship between the sync signals and the data will always be the same.

    Did I go wrong somewhere? Is it better to set the phase difference to 0 and then rotate the data with "rx_channel_data_align"? I have written a piece of code to do just this, but then deemed it useless, because of the relationship of the data and sync signals.
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