Results 1 to 5 of 5

Thread: Query regarding Simulation in Modelsim

  1. #1
    Join Date
    Apr 2017
    Posts
    6
    Rep Power
    1

    Post Query regarding Simulation in Modelsim

    Dear friends,
    I have a query regarding simulation in Modelsim, I want to take a flop of a input signal to introduce a one clock cycle delay, but I didn't get one clock cycle delay in Modelsim.
    So, my question is why I didn't get any delay? If any one have idea about this , please explain me.
    I have attached image of simulation below and also write code for the same.


    RTL:

    `timescale 1ns/100ps


    module flops(
    input logic clk,
    input logic reset_n,
    input logic RxD_in
    );




    logic RxD_in_f1; //first flop of input signal
    logic RxD_in_f2; //second flop of input signal



    always_ff@(posedge clk or negedge reset_n)
    begin
    if ( ~reset_n )
    begin
    RxD_in_f1 <= 1'b0;
    end
    else
    begin
    RxD_in_f1 <= RxD_in;
    end
    end


    always_ff@(posedge clk or negedge reset_n)
    begin
    if(~reset_n )
    begin
    RxD_in_f2 <= 1'b0;
    end
    else
    begin
    RxD_in_f2 <= RxD_in_f1;
    end
    end
    endmodule

    Testbench:



    `timescale 1ns/100ps


    module flops_tb;
    logic clk = 1'b1, reset = 1'b1;
    logic RxD;




    flops inst(
    .clk(clk),
    .reset_n(reset),
    .RxD_in(RxD)
    );


    always
    #1 clk <= ~clk;




    always
    begin
    RxD = 1'b0;
    #10
    RxD = 1'b1;
    #10
    RxD = 1'b0;
    end


    endmodule
    Attached Images Attached Images

  2. #2
    Tricky is offline Moderator **Forum Master**
    Join Date
    Oct 2008
    Posts
    5,763
    Rep Power
    1

    Default Re: Query regarding Simulation in Modelsim

    That will be because you're using absolute time delays in the driver, and not synchonising with the clock. Hence the assignmenst to RxD happen just before the clock edge occurs, and it appears to be an immediate transfer. I suggest using @(posedge clk) in the driver:

    Code:
    always
    begin
    RxD = 1'b0;
    repeat(10) @(posedge clk);
    RxD = 1'b1;
    repeat(10) @(posedge clk);
    end
    I removed the final assignment to 0 as this was ignored - it is an always block and loops forever.

  3. #3
    Join Date
    Apr 2017
    Posts
    6
    Rep Power
    1

    Thumbs up Re: Query regarding Simulation in Modelsim

    Quote Originally Posted by Tricky View Post
    "Hence the assignment to RxD happen just before the clock edge occurs, and it appears to be an immediate transfer."
    Thank you very much I try this ans it works proper.
    But I did'nt get your point mentioned in quotes. Can you please explani this, as we see in wave form RxD rises or falls with clock edge.
    I also wan to ask you that if we use different simulator then is it possible to get different outputs.

  4. #4
    Tricky is offline Moderator **Forum Master**
    Join Date
    Oct 2008
    Posts
    5,763
    Rep Power
    1

    Default Re: Query regarding Simulation in Modelsim

    The problem here is in the code, not in the simulator.
    Simulations are executed using "delta cycles" which are meant to be infinitely small divisions of time. Anyone signal can only have 1 value in any given delta cycle. So in your example, you have set the clock to change from 0 -> 1 after 2 ns. Your data changes from 0 -> 1 after 10 ns. At 10ns, the clock also changes from 0 to 1, giving a clock edge. But the edge is detected at the same time that RxD has also been set to 1, so it is detected as 1.

    so at 10 ns, what occurs is (when using your original code)
    delta 1: clk = 0, RxD = 0
    detla 2: clk = 1, RxD = 1 (clock edge detected, use the value of RxD now, which is 1)

    If you synchronise to the clock, the Assignment to RxD doesnt happen until 1 delta after the rising edge
    delta 1 : clk = 0, RxD = 0
    delta 2 : clk = 1, RxD = 0 (clock edge occurs, read value of RxD, schedule RxD to be set to 1
    delta 3 : clk = 1, RxD = 1

  5. #5
    Join Date
    Apr 2017
    Posts
    6
    Rep Power
    1

    Thumbs up Re: Query regarding Simulation in Modelsim

    Thank you very much sir for your warm reply.
    I got your point.

Similar Threads

  1. simulation with modelsim
    By zaliabbass in forum VHDL
    Replies: 1
    Last Post: August 13th, 2016, 02:32 AM
  2. I need help with simulation by ModelSim
    By yhatagishi in forum VHDL
    Replies: 3
    Last Post: January 24th, 2013, 10:29 PM
  3. Simulation using ModelSim
    By udaysing in forum Quartus II and EDA Tools Discussion
    Replies: 3
    Last Post: June 22nd, 2012, 03:23 AM
  4. ModelSim RTL simulation works, now gate-level simulation
    By goretkin in forum Quartus II and EDA Tools Discussion
    Replies: 0
    Last Post: June 1st, 2011, 08:45 AM
  5. SOPC Simulation with ModelSim Altera vs. ModelSim PE
    By Marlon Winder in forum Quartus II and EDA Tools Discussion
    Replies: 4
    Last Post: May 9th, 2011, 10:19 AM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •