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Thread: Combinational Loop In VHDL synthesis

  1. #11
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    Default Re: Combinational Loop In VHDL synthesis

    Quote Originally Posted by Tricky View Post
    Yes - best case is the design matches your RTL simulation results. Worst case it takes a long time to simulate and doesnt tell you alot.
    Using the RTL only (using best practice) and good timing specs, I have never run a post synthesis simulation - as there has never been a need.
    The only real need these days is for an accurate power analysis using toggle info from the simulation.

  2. #12
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    Default Re: Combinational Loop In VHDL synthesis

    The combinational loops are pretty clear. In your first assignment, PortL0 drives PortR0 and then in your third PortR0 drives PortL0. You of course intend the when clauses to make them mutually exclusive, but I doubt if the tools are that smart. You should use the proper VHDL constructs for mutually exclusive cases:

    Code:
    if(SW='0' and RW='0') then
      PortR0 <= ...
      PortR1 <= ...
      PortL0 <= ...
      PortL1 <= ...
    elsif(SW='0' and RW='1') then
      ...
    elsif(SW='1' and RW='0') then
     ...
    else
     ...
    end if;
    Or a case statement:

    Code:
    	
    	test_proc : process(RW, SW, PortR0, PortL0)
    		variable sel : std_logic_vector(1 downto 0);
    	begin
    	
    		sel := SW & RW;
    	
    		case sel is
    
    		when "00" =>
    			PortR0 <= PortL0;
    			PortL0 <= 'Z';
    		when "01" =>
    			PortL0 <= PortR0;
    			PortR0 <= 'Z';
    		when others =>
    			PortR0 <= 'Z';
    			PortL0 <= 'Z';
    		end case;
    	
    	end process;
    You could still run into trouble though with multiple drivers at a higher level.

    It's not entirely clear what you are trying to do, but inout's are best avoided.

  3. #13
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    Default Re: Combinational Loop In VHDL synthesis

    Yeah. I had also seen this kind of implementation but I didn't know there were a preference for this. Thanks anyway. I will test it.
    As I mentioned in my former posts, I want to build a bidirectional interconnection network between some processors and some memories. This is just sample of my interconnection and I wanted to solve the combinational loop issue.

  4. #14
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    Default Re: Combinational Loop In VHDL synthesis

    Project does have an ELF file. Please make sure project has been buil succcessfully

  5. #15
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    Default Re: Combinational Loop In VHDL synthesis

    Quote Originally Posted by Reza M. Shahshahani View Post
    Yeah. I had also seen this kind of implementation but I didn't know there were a preference for this. Thanks anyway. I will test it.
    As I mentioned in my former posts, I want to build a bidirectional interconnection network between some processors and some memories. This is just sample of my interconnection and I wanted to solve the combinational loop issue.
    Point taken. Buses between chips is one of the few cases where bidirectional lines may make sense since it saves board traces. Of course, you lose the possibility of sending and receiving at the same time and will have all sort of coordination issues unless you have one master.

    I think the case statements (or if/else) actually make the code much more clear since it makes it obvious what the outputs are for a given set of inputs (SW and RW in your case).

  6. #16
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    Default Re: Combinational Loop In VHDL synthesis

    Quote Originally Posted by Reza M. Shahshahani View Post
    Dear all
    I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or Write) and one for switching (like a crossbar switch). To build up the network I need to connect these modules together via their inout data ports. I want to be able to transfer data bidirectionally. I have included my code at the end. This code just has two modules connected to each other.
    - After synthesis in Quartus, ISE, or Synopsys Design Compiler or Synplify Pro, I get warnings which says there are a lot of nodes with combinational loop. But Why? Have I done anything wrong?
    Your entire design is asynchronous because there is no clock.

    You use tristates in internal logic (not connected to I/O pins), and the fabric does not have internal tristates, so the synthesis tool attempts to implement your logic using multiplexers.

    When it does that, because your design is asynchronous, combinatorial loops are created. If you look at the netlist output from the synthesis tool, you might see that.

    The solution is to code this properly: don't use internal tristates, use proper muxes, and make sure you don't have logic loops.

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