# Thread: Convert AHDL to Verilog

1. Altera Beginner
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Oct 2017
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## Convert AHDL to Verilog

I have a design in AHDL for a keyboard scanner and I'm trying to convert this to Verilog.
The AHDL code is in the enclosed ZIP "kbd.zip". The Verilog code is shown hereunder.

The line "assign lresult = (sensecount == i) && sense[7 - i];" gives an error that lresult is driven by multiple gates. Anyone an idea how I can solve that?
Further remarks about the Verilog code also welcome.

Thanks

// Input Port Declarations
input sync;
input mosi;
input eesel_n;
input [7 : 0] sense;

// Output Port Declarations
output result;
output [15 : 0] drv;

// Internal variables
reg [15 : 0] drvcount;
reg [7 : 0] sensecount;
wire [15 : 0] ldrv;
wire lresult;
genvar i;

always @(posedge sync)
begin
if (!eesel_n) drvcount <= 0;
else drvcount <= drvcount + 1;
end

for (i=0;i<15;i=i+1)
begin
assign ldrv[i] = (drvcount == i);
end
assign drv = !ldrv;

always @(negedge advance or posedge sync)
begin
if(sync) sensecount <= 0;
else sensecount <= sensecount + 1;
end

for (i=0;i<7;i=i+1)
begin
assign lresult = (sensecount == i) && sense[7 - i];
end

assign result = (eesel_n)? lresult : 1'bZ;

endmodule

2. Moderator **Forum Master**
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## Re: Convert AHDL to Verilog

Shouldnt lresult be a 6 bit vector. Otherwise lresult is being driven by each iteration of the for loop.

If you didn't know, xilinx ise used to ship with an ahdl to vhdl/verilog translater. Xhdl I think.

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