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Thread: Cyclone V Hard Memory Controller MPFE bandwidth

  1. #1
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    Default Cyclone V Hard Memory Controller MPFE bandwidth

    I have a QSYS design which uses DDR memory. The DDR memory is clocked at 400Mhz in the Hard Memory Controller, and is 32 bits wide, so max bandwidth (not allowing any latency!) is 2*400,000,000*32 = 25.6Gbps.
    I then connect the Multi-Port Front-End (MPFE) controller of the HMC up by setting 2 ports, both 128 bits wide, bidirectional. There are clocked at 168MHz, so theoretical bandwidth on each of these is 128bits * 168MHz = 21.5Gbps.

    I now have some VIP suite Frame Buffers hooked up and I run into bandwidth problems. I start with 1 frame buffer enabled, processing 1080p60 video, which is 1920x1080x20 (bits per pixel) x 60 (frames per second) = 2.5Gbps. The Frame buffer has a read and a write port, so we actually need 5Gbps. Running 1 frame buffer at 1080p60 is fine. If I enable a second one though, they both struggle for bandwidth (it seems) as the video breaks up. Given that we're at 2/5 bandwidth of the DDR memory itself, and around 1/2 bandwidth of one AVL interface to the MPFE we should be fine. I have another design that this works fine with, but I cannot get it to work in this one.

    If anyone could check my bandwidth calcs, and/or explain why I would be limited in my bandwidth then I'd greatly appreciate it.

    Cheers,
    Simon
    (Copied from FPGA forum as it's probably better hosted here - moderators feel free to delete the thread from the FPGA forum - unless of course someone has responded to it in there in the meantime).

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    Default Re: Cyclone V Hard Memory Controller MPFE bandwidth

    Hi Simon,

    I am facing same issues with a Cyclone V GT board. Have you managed to solve the issue, yet? Please let me know.


    Kind regards,

    Lijo

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    Default Re: Cyclone V Hard Memory Controller MPFE bandwidth

    Not entirely, there was some issue between how the two ports were shared between the various things using them, so that was tidied up, and we then made some compromises in terms of what resolutions one pipe ran at, etc. I seem to also remember there was some error in my calculations of actual available bandwidth to/from the MPFE ports, but haven't got the calculations with me.

    Good luck with your design,
    Simon

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    Default Re: Cyclone V Hard Memory Controller MPFE bandwidth

    I assume this is efficiency issue
    This should be expected because the controller efficiency will drop when we are using more than one port (MPFE).
    https://www.altera.com/support/suppo...02012_952.html

    Based on your calculation, you assume the efficiency is 100% which is impossible for a memory controller.

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    Default Re: Cyclone V Hard Memory Controller MPFE bandwidth

    Quote Originally Posted by boonchie View Post
    Based on your calculation, you assume the efficiency is 100% which is impossible for a memory controller.
    True, the calculations expect 100% efficiency, but a) no figure is given for expected efficiency, and b) I suggest that I might be using 40% of the maximum efficiency, and if the MPFE design is that poor I'd be very surprised.

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