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Thread: assign two clocks

  1. #11
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    Default Re: assign two clocks

    You have not specified a target for your create_generated_clock constraint. That's why it's coming up as a virtual clock. If you are using a PLL, the target should be the output clock pin (get_pins) of the PLL, or just use derive_pll_clocks as mentioned.

  2. #12
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    Default Re: assign two clocks

    I don't use a PLL or input/output pins as it's a simple internal clock divider. I really don't know how to resolve these warnings.

  3. #13
    Tricky is offline Moderator **Forum Master**
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    Default Re: assign two clocks

    Quote Originally Posted by Binome View Post
    I don't use a PLL or input/output pins as it's a simple internal clock divider. I really don't know how to resolve these warnings.
    The simplest and least problem clock divider is a PLL. A logic based clock divider can cause lots of timing problems as you can get a lot of skew on it. A PLL is almost always the simplest and best solution (not least as the constraints come for free with the derrive_pll_clocks SDC command)

  4. #14
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    Default Re: assign two clocks

    OK, I'll try that but I have not the time today.

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