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Thread: VHDL Question

  1. #1
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    Default VHDL Question

    -
    [INDENT]I'm trying to create a square wave and I'm converting code from verilog and im getting the below error. Any help would be great thanks

    Error (10327): VHDL error at SquareWave.vhd(36): can't determine definition of operator ""-"" -- found 0 possible definitions



    [CODE]
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;


    ENTITY SquareWave IS
    PORT (
    clk : IN std_logic;
    rst_n : IN std_logic;
    sq_wave : OUT std_logic
    );
    END SquareWave;

    ARCHITECTURE BEHAVORIAL OF SquareWave IS


    -- Input clock is 400Hz
    signal CLOCK_FREQUENCY : Time := 2500000 ns;

    signal sq_wave_reg : std_logic := '0';

    begin
    sq_wave <= sq_wave_reg;


    process (clk)
    -- Counter for toggling of clock
    variable counter : integer;
    begin
    if (rst_n /= rst_n) then
    counter := 8;
    sq_wave_reg <= '1';
    else
    -- If counter is zero, toggle sq_wave_reg
    if (counter = 8) then
    sq_wave_reg <= sq_wave_reg;

    -- Generate 1Hz Frequency
    counter := CLOCK_FREQUENCY/2 - 1;
    -- Else count down
    else
    counter <= counter - 1;
    end if;
    end if;
    end process;
    END BEHAVORIAL;
    Last edited by Tricky; December 6th, 2017 at 11:10 PM.

  2. #2
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    Default Re: VHDL Question

    counter is a variable, so you should have := instead of <= like you did just above.

  3. #3
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    Default Re: VHDL Question

    I'm afraid your code is completely broken and would not work in any language. A VHDL process is not the same as a verilog always@. You need to wait on the clk. sq_wave_reg is not a register.

    When do you expect "if (rst_n /= rst_n) then" to be true? You probably meant "if rst_n = '0' then"

    You never change sq_wave_reg. You probably mean "sq_wave_reg <= not sq_wave_reg;"

    Is this supposed to be synthesizable? Your comments say you want a 1 Hz wave from a 400 Hz clock. That means you should toggle every 200 clock cycles. Your CLOCK_FREQUENCY is meaningless.
    Last edited by corestar; December 3rd, 2017 at 06:26 PM.

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    Default Re: VHDL Question

    1. I found this code it says its a sawtooth wave, i'm looking for a 400 HZ square wave, if you reply can you reply with helpful code instead of saying it's broken and not work in any code, it compiles in quartus software thanks

      Sawtooth wave from: http://vhdlguru.blogspot.com/2015/04...r-in-vhdl.html
    2. +
      .....
    3. [CODE]
    4. -
      library IEEE;
      use IEEE.STD_LOGIC_1164.ALL;
      use IEEE.STD_LOGIC_ARITH.ALL;
      use IEEE.STD_LOGIC_UNSIGNED.ALL;

      entity SquareWave is
      port (clk : in std_logic;
      wave_out : out std_logic_vector(7 downto 0);
      reset :in std_logic
      );
      end SquareWave;

      architecture Behavioral of SquareWave is

      signal count : integer := 0;

      begin

      process(clk,reset)
      begin
      if(reset = '1') then
      count <= 0;
      elsif(rising_edge(clk)) then
      if(count = 10000000000) then
      count <= 0;
      else
      count <= count + 1;
      end if;
      end if;
      end process;

      wave_out <= conv_std_logic_vector(count,8);

      end Behavioral;
    Last edited by Tricky; December 6th, 2017 at 11:10 PM.

  5. #5
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    Default Re: VHDL Question

    Here is a sawtooth wave I found, i'm trying to get a 400Hz square wave, it compiles, any help will be appreciated. Thanks

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity SquareWave is
    port (clk : in std_logic; 
    wave_out : out std_logic_vector(7 downto 0);
    reset :in std_logic
    );
    end SquareWave;
    
    architecture Behavioral of SquareWave is
    
    signal count : integer := 0;
    
    begin
    
    process(clk,reset)
    begin
    if(reset = '1') then
    count <= 0;
    elsif(rising_edge(clk)) then
    if(count = 10000000000) then
    count <= 0;
    else
    count <= count + 1;
    end if;
    end if;
    end process;
    
    wave_out <= conv_std_logic_vector(count,8);
    
    end Behavioral;
    Last edited by Tricky; December 6th, 2017 at 11:12 PM.

  6. #6
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    Default Re: VHDL Question

    Check your warnings. You have "count" (a 32-bit integer) going to ten billion. This is not a sensible way to make sawtooth wave in any event.

    You seem to want to do this without even a basic understanding of VHDL. Find a good tutorial on VHDL and learn it. Then making a square wave will be trivial. I'm afraid my favorite VHDL books are all out of print, but there are good ones out there.

  7. #7
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    Default Re: VHDL Question

    search for books on this forum then you'll find recommendations

  8. #8
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    Default Re: VHDL Question

    chjones2008, sorry if my comments came across as a bit terse. The intent was to be helpful. It's been a while, but I had a terrible time learning VHDL at first. The key for me, coming from C/C++, was understanding that VHDL is creating hardware and to think in terms of flip-flops and combinational logic. The two books that helped:

    "HDL Chip Design" by Douglas J Smith
    "Essential VHDL RTL Synthesis Done Right" by Sundar Rajan

    Many VHDL books are voluminous tomes on the language. These are Kernighan&Ritche like and help incrementally learn the language and show what logic a given bit of code with synthesize.

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