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Thread: 1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

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    Default 1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

    I need to drive multiple 1.8V HSTL differential pairs from a Cyclone 10 LP FPGA. The output is DDR, source synchronous.

    I am currently doing this with single-ended signals using the ALTDDIO_OUT megafunction. How do I best make each output pin differential instead of single-ended?

    From the datasheet, I believe that only the CLKOUT pins support differential HSTL output. So, I must emulate it with two single-ended outputs with one inverted.

    I don't seem to be able to tell the pin planner to make the pins a pair (like we do for LVDS).

    Any guidance is much appreciated!

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    Default Re: 1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

    Sorry for the original question being confusing. My basic question is how can I use the DDR output registers (thru ALTDDIO_OUT) to drive two pins in a pseudo-differential fashion (one inverted from the other)? What is the suggested approach? I don't think we can invert the output of the ALTDDIO for the negative pin.

    Specifically, I'm targeting a Cyclone 10 LP FPGA, with VHDL using Quartus Prime v17.1.

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    Default Re: 1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

    According to the device handbook, 1.8V differential HSTL standard is supported on all IO banks. No need to simulate anything, just assign a pin pair to the logical port.

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    Default Re: 1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

    Thank you for your reply, FvM.

    I originally tried to do as you suggest. The pin-planner does not give me the option of 1.8V Differential HSTL Class I on most I/O pins. Digging further in the "Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook", pg 102 says:

    The following differential I/O standards are supported only on clock input pins and
    PLL clock output pins:
    Differential SSTL-2 and Differential SSTL-18
    Differential 1.8 V HSTL, Differential 1.5 V HSTL, and Differential 1.2 V HSTL

    So, I believe I cannot use the differential output standards on normal I/O pins. Or is there something I'm overlooking?


    Ultimately, I'm needing 5 differential output pairs to drive a MIPI CSI-2 output. The Altera app note: "AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs" recommends using the differential 1.8V HSTL outputs.

    Maybe the closest I can come is using two single ended 1.8V HSTL outputs. What do you all think? Then my question is how to drive them both from a ALTDDIO_OUT megafunction?

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    Default Re: 1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

    Thank you for your reply, FvM.

    I originally tried to do as you suggest. The pin-planner does not give me the option of 1.8V Differential HSTL Class I on most I/O pins. Digging further in the "Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook", pg 102 says:

    The following differential I/O standards are supported only on clock input pins and
    PLL clock output pins:
    Differential SSTL-2 and Differential SSTL-18
    Differential 1.8 V HSTL, Differential 1.5 V HSTL, and Differential 1.2 V HSTL

    So, I believe I cannot use the differential output standards on normal I/O pins. Or is there something I'm overlooking?


    Ultimately, I'm needing 5 differential output pairs to drive a MIPI CSI-2 output. The Altera app note: "AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs" recommends using the differential 1.8V HSTL outputs.

    Maybe the closest I can come is using two single ended 1.8V HSTL outputs. What do you all think? Then my question is how to drive them both from a ALTDDIO_OUT megafunction?

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