Results 1 to 3 of 3

Thread: Instantiate VHDL Generics with Verilog code (for testbench)

  1. #1
    Join Date
    Feb 2018
    Rep Power

    Post Instantiate VHDL Generics with Verilog code (for testbench)

    Hello everybody.

    When I instanciate inputs and outpus of a verilog code with verilog testbench I use following structure:

    name_module MUT( .input_1(input_1),
    And I instanciate params with this strucure:

    defparam MUT.name_param = value.

    But I have a problem when module under test is VHDL code and testbench is verilog code. ModelSim fail when I use defparam for instanciate generics VHDL.

    Somebody can say me the instruction for instanciate generics VHDL with verligo testbench?


  2. #2
    Join Date
    Jun 2007
    Rep Power

    Default Re: Instantiate VHDL Generics with Verilog code (for testbench)


    Just use the normal verilog method
     # ( <verilog parameters/vhdl generics> ) 
    <instance_name> (
    You don't need to use defparam.

  3. #3
    Tricky is offline Moderator **Forum Master**
    Join Date
    Oct 2008
    Rep Power

    Default Re: Instantiate VHDL Generics with Verilog code (for testbench)

    Defparam is explicitly forbidden in the Modelsim User Manual for instantiating VHDL inside a Verilog testbench:

    Quote Originally Posted by Modelsim User Manual
    Generic Associations
    Generic associations are provided via the module instance parameter value list. List the values
    in the same order that the generics appear in the entity. Parameter assignment to generics is not
    case sensitive.

    The defparam statement is not allowed for setting generic values.

Similar Threads

  1. Replies: 13
    Last Post: January 6th, 2018, 04:16 AM
  2. Instantiate System Verilog into a VHDL Testbench
    By michalaj in forum General Altera Discussion
    Replies: 6
    Last Post: September 23rd, 2015, 09:37 PM
  3. Help with verilog testbench code
    By defeduma in forum Verilog and System Verilog
    Replies: 1
    Last Post: November 25th, 2013, 02:31 AM
  4. How to write testbench(VHDL and Verilog HDL)
    By hapyang in forum Shared Material
    Replies: 2
    Last Post: May 6th, 2010, 12:30 AM
  5. how to implement a VHDL testbench for verilog module?
    By mayp in forum Quartus II and EDA Tools Discussion
    Replies: 7
    Last Post: June 4th, 2009, 12:44 AM


Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts