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Thread: Instantiate VHDL Generics with Verilog code (for testbench)

  1. #1
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    Post Instantiate VHDL Generics with Verilog code (for testbench)

    Hello everybody.

    When I instanciate inputs and outpus of a verilog code with verilog testbench I use following structure:

    name_module MUT( .input_1(input_1),
    .input_2(input_2),
    .output_1(output_1),
    .output_2(output_2)
    );
    And I instanciate params with this strucure:

    defparam MUT.name_param = value.

    But I have a problem when module under test is VHDL code and testbench is verilog code. ModelSim fail when I use defparam for instanciate generics VHDL.

    IN CONCLUSION:
    Somebody can say me the instruction for instanciate generics VHDL with verligo testbench?

    Thanks

  2. #2
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    Default Re: Instantiate VHDL Generics with Verilog code (for testbench)

    Hi,

    Just use the normal verilog method
    Code:
     <module_name> 
     # ( <verilog parameters/vhdl generics> ) 
    
    <instance_name> (
    
    );
    You don't need to use defparam.

  3. #3
    Tricky is offline Moderator **Forum Master**
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    Default Re: Instantiate VHDL Generics with Verilog code (for testbench)

    Defparam is explicitly forbidden in the Modelsim User Manual for instantiating VHDL inside a Verilog testbench:

    Quote Originally Posted by Modelsim User Manual
    Generic Associations
    Generic associations are provided via the module instance parameter value list. List the values
    in the same order that the generics appear in the entity. Parameter assignment to generics is not
    case sensitive.

    The defparam statement is not allowed for setting generic values.

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