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Thread: PLL's in Cyclone V

  1. #1
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    Default PLL's in Cyclone V

    Hello,

    I am trying to use the output of a PLL to drive a logic in FPGA. I'm not sure which clock should be connected as the 'refclk' for the PLL and how the 'outclk' of the PLL should clock my logic.
    I have tried using a 50MHz clock (PIN AF_14) as a refclk for the PLL, and used the PLL 'outclk' as a clock input but my logic does produce any output. Could you please help?
    Also, when I check my logic in ModelSim, the correct results are obtained.

    Thank you.
    Last edited by sudhee2893; February 10th, 2018 at 07:12 PM.

  2. #2
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    Default Re: PLL's in Cyclone V

    Hi,

    Are you using development kit?
    Check/Monitor the clock 50Mhz refclk input Using signal-tap for the debug.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)

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    Default Re: PLL's in Cyclone V

    Hi Anand,

    I used the Signal Tap to monitor the refclk of PLL and looks like it is not being clocked. Seems strange as I connected the top level input clock port to the instantiated PLL (Altera-PLL).
    I think I am missing some information about dedicated clocks for PLL's.

    The board is Arrow SoCkit evaluation with Cyclone 5. Board Number: 5CSX5C6D631C6

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    Default Re: PLL's in Cyclone V

    Hi,

    Reference clock pin is wrong.
    Assign AC18 and check.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)

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    Default Re: PLL's in Cyclone V

    Hello Anand,

    Since my logic output is being sent to a HSMC pin (Bank 8A), I am using clock K14 now which is a dedicated PLL clock input (this is being used a refclk), could you help me understand how the connections are to be made to the PLL dedicated clock output (PIN A10 or A11) which can be used as the PLL 'clkout' to drive my logic.

    Thanks a lot for your help.

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    Default Re: PLL's in Cyclone V

    Hi,

    Do you have any daughter card connected to board?(In HSMC interface)?

    Because K14 pin is not having any oscillator on board,It should be from daughter cards.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)

  7. #7
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    Default Re: PLL's in Cyclone V

    Hi,

    The clocks on your board are derived from the Si5338 Oscillator . The pins that are connected to the FPGA are : Y26, AF14, AA16, K14. These are the 50MHz clocks that are connected from the Si5338 to the FPGA. You could try any of these. These are the clock assignments from the QSF file for the board..

    set_location_assignment PIN_Y26 -to clk_100m_fpga
    set_location_assignment PIN_K14 -to clk_50m_fpga
    set_location_assignment PIN_AA16 -to clk_top1
    set_location_assignment PIN_AF14 -to clk_bot1

    set_location_assignment PIN_AA26 -to hsmc_clkin_p[1]

    set_location_assignment PIN_H15 -to hsmc_clkin_p[2]

    set_location_assignment PIN_E7 -to hsmc_clkout_p[1]

    set_location_assignment PIN_A11 -to hsmc_clkout_p[2]
    set_location_assignment PIN_J14 -to hsmc_clk_in0
    set_location_assignment PIN_AD29 -to hsmc_clk_out0

    After making the pin assignments, you need to make sure that the PLL in your design is using the clock from the mentioned pins. Also check if there are any Jumpers/ settings for clock selection on the board.
    Last edited by eapenabrm; February 12th, 2018 at 08:26 PM.

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    Default Re: PLL's in Cyclone V

    Hello eapenabrm,

    I measured the outclk of the PLL using Signal Tap, looks like it is generating some signal. Although there is no output at the HSMC pin (PIN_B13), this is where I measure the signal for all the logic I have implemented till date (it worked fine up until I started using PLL's). I have attached some screenshots to provide a better perspective of the problem.

    data_out is where I measure the output signal on the HSMC which has a daughter board connected to it.

    Thank you very much for your help.
    Attached Images Attached Images

  9. #9
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    Default Re: PLL's in Cyclone V

    Hi,

    Output will be not available when PLL is not locked.

    Check the PLL configuration.
    If the input clock remains within the minimum and maximum frequency specifications, the PLL is able to
    achieve lock.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)

  10. #10
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    Default Re: PLL's in Cyclone V

    Hi,

    Can you post larger image of the input clocks/ PLL signals and your outputs. Also put in your code in the editor window using "code" blocks so we can take a look at it. Maybe able to help you after we get a better picture of what you are trying to do here.

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