Page 2 of 2 FirstFirst 12
Results 11 to 13 of 13

Thread: Fractional N PLL implimentation in IP possible on Cyclone V and max10?

  1. #11
    Join Date
    Apr 2017
    Posts
    13
    Rep Power
    1

    Default Re: Fractional N PLL implimentation in IP possible on Cyclone V and max10?

    Quote Originally Posted by TCWORLD View Post
    PLLs are largely analogue, not digital. You cannot build a PLL out of digital logic alone, which means you can't build one on an FPGA.
    Thanks, TCWORLD. I thought so.

    I imagine a solution would require interfacing through FPGA I/O to external circuit for analog elements - i think i've read about such circuits that take advantage of FPGA logic with an external circuit component to the function. This is the idea i have in mind.

    For the sake of example, lets say i am able to connect an external circuit to Max10 I/O pins to create an 'inboard/outboard' PLL for the Max to access, thereby minimizing outside world and possibly lowering noise. I haven't had a lot of experience with FPGA but this seems like a good idea. Does this make sense? I'm pondering whether i could even build a fractional N function into this 'inboard/outboard' PLL...
    Last edited by BillyZDSP; February 15th, 2018 at 01:27 PM.

  2. #12
    Daixiwen is offline Moderator **Forum Master**
    Join Date
    May 2008
    Location
    Norway
    Posts
    4,473
    Rep Power
    1

    Default Re: Fractional N PLL implimentation in IP possible on Cyclone V and max10?

    I have a hard time imagining how you could use some simple analog off chip circuitry to raise the frequency of your clock from 50 Hz to 5MHz in order to use the PLL. I guess that you could have a succession of selective filters that would work on harmonics but I wouldn't call that solution simple, elegant, or low noise/jitter, if it can even work in the first place.
    If you already have a solution with an external chip that works well maybe you should keep it.
    It may be a stupid question but why do you need that in the first place? Couldn't you use a normal crystal oscillator and use logic to synchronize to the 50 Hz input instead? Do you really need that clock to be exactly 10^6 times the frequency of the input clock?
    Definition of a man-year: 730 people trying to finish the project before lunch

  3. #13
    Join Date
    Apr 2017
    Posts
    13
    Rep Power
    1

    Default Re: Fractional N PLL implimentation in IP possible on Cyclone V and max10?

    Quote Originally Posted by Daixiwen View Post
    I have a hard time imagining how you could use some simple analog off chip circuitry to raise the frequency of your clock from 50 Hz to 5MHz in order to use the PLL. I guess that you could have a succession of selective filters that would work on harmonics but I wouldn't call that solution simple, elegant, or low noise/jitter, if it can even work in the first place.
    If you already have a solution with an external chip that works well maybe you should keep it.
    It may be a stupid question but why do you need that in the first place? Couldn't you use a normal crystal oscillator and use logic to synchronize to the 50 Hz input instead? Do you really need that clock to be exactly 10^6 times the frequency of the input clock?
    Thanks, Daixiwen. I'm sure you're right about just using the chip solution i have. Creating a soft IP version of the chip for FPGA is not my first task. Just something that occurred to me.

    Yes, i need to sync 10^6 for my application. I'm interested in your idea - use a normal crystal oscillator and use logic to synchronize. It sounds hopeful, but i'm not sure it will work for my application - can you elaborate or point me to a reference? I'm interested in all ideas. Thanks for your help.

    I need locked at the 10^6 input, but absolute phase not necessary - for every single cycle at 50Hz. i need 50M evenly spaced cycles. Phase locked also acceptable.

    Cheers,

Similar Threads

  1. Fractional pll reconfig on cyclone v - share with mux
    By foft in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 0
    Last Post: January 5th, 2017, 01:22 PM
  2. Cyclone V LVDS fractional PLL
    By vanoDNK in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 7
    Last Post: May 25th, 2015, 09:38 PM
  3. Replies: 1
    Last Post: March 17th, 2015, 03:21 AM
  4. Fractional PLL Drifting Cyclone V
    By randolina in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 0
    Last Post: March 21st, 2014, 07:01 AM
  5. UART Implimentation Help
    By clericnmf in forum General Altera Discussion
    Replies: 5
    Last Post: November 17th, 2008, 09:56 PM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •