Results 1 to 3 of 3

Thread: Error (169281): There are 469 IO input pads in the design

  1. #1
    Join Date
    Mar 2018
    Location
    Sweden
    Posts
    2
    Rep Power
    1

    Default Error (169281): There are 469 IO input pads in the design

    I get the following error message in Quartus when I compile my code:

    Error (169281): There are 469 IO input pads in the design, but only 293 IO input pad locations available on the device.

    However it works fine when I compile the same VHDL code in VT System FPGA Manager (Vector tool).

    I am using Cyclone IV E EP4CE75F23I8L.

    Since I am using a Vector board there are a number of IO ports that are set by default in the main HDL file. Do I get this error because Quartus does not know which board I intend to use?

    Also, is the error message referring to the IO pads available on the FPGA or on the board?

  2. #2
    Join Date
    May 2013
    Posts
    848
    Rep Power
    1

    Default Re: Error (169281): There are 469 IO input pads in the design

    Quartus doesn't know anything about your board. Check the Pin Planner to make sure your I/O location assignments are set correctly, but it clearly seems like there are too many I/O in your design for the device you are targetting. I don't know what VT System FPGA Manager is (is that a synthesis tool?).

  3. #3
    Join Date
    Mar 2018
    Location
    Sweden
    Posts
    2
    Rep Power
    1

    Default Re: Error (169281): There are 469 IO input pads in the design

    Quote Originally Posted by sstrell View Post
    Quartus doesn't know anything about your board. Check the Pin Planner to make sure your I/O location assignments are set correctly, but it clearly seems like there are too many I/O in your design for the device you are targetting. I don't know what VT System FPGA Manager is (is that a synthesis tool?).

    VT System FPGA Manager is a tool from the company Vector that executes Quartus for compilation of the VHDL code, and uses its board as target. When I do it directly on Quartus it doesn't know anything about my board so I should probably stick to the VT System FPGA Manager but the problem is that the compilation takes forever (over 1.5 hours) and I had to cancel because I couldn't wait for it so long.

    However compiled a similar design before, and it only took 20 minutes, don't know why It takes so much time now. It is almost the same design. Just added some input ports.

Similar Threads

  1. Recommended pads for UBGA-169
    By noam_tz in forum General Altera Discussion
    Replies: 2
    Last Post: July 20th, 2016, 04:35 AM
  2. Error: Input port must be driven by a non-inverted input pin or another PLL
    By a52581120 in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 3
    Last Post: December 14th, 2011, 06:30 PM
  3. PADS Schematic symbol for EP4SGX530KF43C2
    By pkkeng in forum General Altera Discussion
    Replies: 0
    Last Post: July 12th, 2011, 01:02 AM
  4. Pads too close error with DAC daughter card
    By ThomasMcLeod in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 0
    Last Post: May 26th, 2011, 04:23 PM
  5. Setting termination for I/O pads
    By jefflieu in forum Quartus II and EDA Tools Discussion
    Replies: 5
    Last Post: July 7th, 2010, 10:54 PM

Tags for this Thread

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •