I know the traditional way to convert binary fractions (fixed) to decimal notation. The traditional way is below:


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[-A-] Traditional technique for converting decimal number 0.42
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step 1: 0.47 * 2 = 0.94 ; store integral part: 0
step 2: 0.94 * 2 = 1.88 ; store integral part: 1
step 3: 0.88 * 2 = 1.76 ; store integral part: 1
step 4: 0.76 * 2 = 1.52 ; store integral part: 1
step 5: 0.52 * 2 = 1.04 ; store integral part: 1
[-B-]final answer: 0.01111......


Question: Can I get the final answer [-B-] using shift operation ? I am looking for something similar to Double Dabble. I don't want to use [-A-] because I'm trying to avoid the Multiplication core in an FPGA. Multiplication core just takes extra clock cycles for each multiplication operation and I'd like to avoid that.


[-C-] Summary:
1. Decimal/BCD (whole) --- > Binary : use Reverse Double Dabble.
2. Decimal/BCD (fraction) --- > Binary : ????? (I don't want to use [-A-])
3. Binary(whole) --- > Decimal/BCD : use Double Dabble
4. Binary(fraction) --- > Decimal/BCD : use Reverse Double Dabble.


For [-C-].2, I'm trying to find/come up with a technique similar to [-C-].1, [-C-].3, and [-C-].4. Any suggestions?