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Thread: About My VHDL Task

  1. #1
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    Default About My VHDL Task

    Hi, as a beginner in VHDL, I like to hear comments and ideas from you.

    I have a task to do, my lecturer sent me a code but I couldn't find out.

    This's the code.

    --
    library ieee;
    use ieee.std_logic_1164.all;


    entity singen is
    port
    (
    clk : in std_logic;
    q : out std_logic_vector(7 downto 0)
    );
    end entity;


    architecture rtl of singen is


    type regtype IS array (0 to 15) of std_logic_vector(7 downto 0);

    signal reg : regtype :=
    (X"00", X"18", X"2d", X"3b", X"40", X"3b", X"2d", X"18",
    X"00", X"e8", X"d3", X"c5", X"c0", X"c5", X"d3", X"e8");


    signal c : integer range 0 to 15 := 0;

    begin


    process
    begin
    wait until rising_edge(clk);
    if (c < 15) then
    c <= c + 1;
    else
    c <= 0;
    end if;
    end process;


    q <= reg(c);


    end rtl;
    --
    He told me that "Use this file as component in VHDL and create design, where two sinusoidal signals with different frequencies (31250 Hz and 78125 Hz) are summed or subtracted (depending on outside signal)."

    With this above code how to generate two signals with different frequencies. It's generating only one signal and it's being q. But I don't know how he adjusted its frequency like he desired. Do you guys mind if explaining me? Thanks in advance.

  2. #2
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    Default Re: About My VHDL Task

    Do you remember your ;ecturer telling you about adders? hlw about prescalers? Clock frequencies?

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    Default Re: About My VHDL Task

    Quote Originally Posted by PietervanderStar View Post
    Do you remember your ;ecturer telling you about adders? hlw about prescalers? Clock frequencies?
    I know how to make prescalers and to define frequency of clock signal. But, something that I don't know and he didn't bring up, why 'c' is assumed till 15, why not 20. I again know there's frequency calculation with this whole number, but how to calculate it we haven't learnt. That's what I posted.

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    Tricky is offline Moderator **Forum Master**
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    Default Re: About My VHDL Task

    The reg table only has 16 elements. It does seem a design flaw to count only from 0 to 14, rather than 0 to 15. It cannot run until 20 because it would overflow the reg array.

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    Default Re: About My VHDL Task

    Quote Originally Posted by Tricky View Post
    The reg table only has 16 elements. It does seem a design flaw to count only from 0 to 14, rather than 0 to 15. It cannot run until 20 because it would overflow the reg array.
    I didn't mean that. The prescaler should be meaning and adjusting the frequency. If it has ability to count to 20(such as), This situation will be changing the frequency. There should be a calculation why he has 16 elements.

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    Default Re: About My VHDL Task

    Quote Originally Posted by huytergan View Post
    There should be a calculation why he has 16 elements.
    because that resolution of the sine is good enough for the purpose of the assignment I think.

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    Default Re: About My VHDL Task

    Quote Originally Posted by PietervanderStar View Post
    because that resolution of the sine is good enough for the purpose of the assignment I think.
    Do you mind if telling me the frequency here, isn't it f=1/640000 ps = 1562500 Hz?
    Attached Images Attached Images
    Last edited by huytergan; April 25th, 2018 at 08:36 AM.

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    Default Re: About My VHDL Task

    huytergen,

    You can't do what he asks using the code he sent you. It looks like the reg table is a simple 16 element full sine wave in twos-compliment with an amplitude of 64. You should research DDS (Direct Digital Synthesis) and will find alot of info on the web. The output frequency of a DDS is set by setting a "tuning word" to an appropriate value:

    F = M * Fc / 2^n

    where F is the sine wave frequency, Fc is the clock frequency, M is the tuning word, and n is the width of the phase accumulator in bits. Normally, the phase accumulator is much wider than the lookup table in order to get the desired frequency resolution. For example, if your clock is 100 Mhz and you want a resolution of 1 Hz, set M to 1 to find 2^n of 10.0e8 so you need n = 27. Most people would just use 32 bit for the phase accumulator and M. Then use the upper 4-bits as an index into your lookup table.

    So you will need to change his code to have a phase increment M input into the entity. The way he is incrementing c is very clumsy. It is going from 0 to 15 so it makes much more sense to make it an unsigned 4-bit number that you increment by M in one-line of code. M will also be an unsigned 4-bit number. He has M hardwired to 1, so the output frequency is fixed. In practice, you probably cannot achieve the desires frequencies with a 4-bit phase accumulator and will have to make it much wider.

    You can figure out the rest.
    Last edited by corestar; May 12th, 2018 at 09:58 PM.

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    Default Re: About My VHDL Task

    Quote Originally Posted by corestar View Post
    He has M hardwired to 1, so the output frequency is fixed.
    That is assuming that the clock frequency is fixed. I don't know the level of this course but for beginners changing the clock speed, and given the numbers devide too beautifully to be a coincidence I think just a prescaler will fulfill the requirement, with a verry crude sine, but good enough I think.

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    Default Re: About My VHDL Task

    Quote Originally Posted by PietervanderStar View Post
    That is assuming that the clock frequency is fixed. I don't know the level of this course but for beginners changing the clock speed, and given the numbers devide too beautifully to be a coincidence I think just a prescaler will fulfill the requirement, with a verry crude sine, but good enough I think.
    You're probably right since one freq is 2.5 times the other. If he's lucky, the instructor was showing a clumsy way to do it so they would appreciate the next lesson on how to do it more elegantly .

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