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Thread: Nios II 32-bits read access to a 16-bits SRAM problem

  1. #1
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    Default Nios II 32-bits read access to a 16-bits SRAM problem

    Hi.
    I have a 16-bit data width SRAM (CY62167EV30LL-45BVXI) connected to my FPGA. I want to get NIOS II accessing it.
    The accesses, write or read, are working OK using 8 bits or 16 bits accesses (IORD_8DIRECT and IORD_16DIRECT).
    But when I try to read with a 32 bits access, the values of the bits 0 to 15 came with a repetition of the value that are on bits 16 to 31.
    The problem seems to be just when reading 32bits.
    In the example bellow, I read from 0x80800000 to 0x8080000b using 8 bit (fist line), 16 bits (second line) and 32 bits (third line).

    address 0x80800000: 0 11 22 33 44 55 66 77 88 99 aa bb (12 x IORD_8DIRECT)
    address 0x80800000: 1100 3322 5544 7766 9988 bbaa (6 x IORD_16DIRECT)
    address 0x80800000: 33223322 77667766 bbaabbaa (3 x IORD_32DIRECT)

    The 8bits and 16 bits acesses are OK (first and second lines)
    In the 32 bits access (third line) it is possible to see that the bits 0 to 15 are wrong.

    I am using the NIOS II data_master connected to a "Generic Tri State controller", connected to a "TriState Conduit Pin Sharer", connected to a "Tri-State Conduite Bridge", exported to my VHDL code, and conected to my external SRAM.
    I connected the the address_out(20 downto 1) of the tri_state_conduit_bridge to the address(19 downto 0) of the physical memory. A QSYS print screen is attached.

    Thank you.
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  2. #2
    Join Date
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    Default Re: Nios II 32-bits read access to a 16-bits SRAM problem

    This sounds familiar, unfortunately I don't remember the details but you might be able to fix this by placing a 16-bit pipeline bridge between Nios and the tristate logic.

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