Hello,

I am currently trying to latch data from an ADC that uses LVDS communication (AFE5801, http://www.ti.com/lit/ds/symlink/afe5801.pdf). I'm currently working with a Terasic DE0 Nano SoC.
This is my first time working with LVDS, so I'm looking for some advice on how to start.
I've discovered that I need to use a DDR register and serial-to-parallel shift register to accomplish this. The ALTLVDS_RX function seems to handle this for me, but I had a few questions about how to set this up:

- The ADC has a output frame clock. Is supposed to be the input clock to the ALTLVDS_RX function?
- What reason would you need to use the external PLL setting in the function?
- Since the max deserialization factor setting is 10x, I understand that I need to set the function 6x instead, and load 12bit register over two clock cycles. What exactly are the timing parameters involved with this?

Any examples of the ALTLVDS_RX function in use would be appreciated.

Thanks