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Thread: SystemVerilog logic type as bidir

  1. #1
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    Default SystemVerilog logic type as bidir

    Hello,

    I'm new to SystemVerilog and have a question about a warning Quartus is throwing. I'm working with a design done by someone else.
    In my code I have a 2 interfaces which have port type logic. In the module there is assignment of one logic type to another... for example

    interface typeA();
    logic[3:0][3:0] mem_A;
    endinterface


    interface typeB();
    logic[3:0] b1;
    logic[3:0] b2;
    logic[3:0] b3;
    endinterface

    module dut(typeA in, typeB out);
    assign out.b1[0] = in.mem_A[0];
    assign out.b2[1] = in.mem_A[1];
    assign out.b3[2] = in.mem_A[2];
    endmodule

    I'm trying to get rid of this warning but don't know what do to since the interfaces are being used multiple times all over the design.
    Warning (10665): Bidirectional port "IN.pix[0][2]" at If.sv(47) has a one-way connection to bidirectional port "OUT.grn[0][2]"


    Thanks in advance.

  2. #2
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    Default Re: SystemVerilog logic type as bidir

    The error message has the identifiers 'pix' and 'grn', but they do not exist in the source code.

  3. #3
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    Default Re: SystemVerilog logic type as bidir

    Quote Originally Posted by dave_59 View Post
    The error message has the identifiers 'pix' and 'grn', but they do not exist in the source code.
    The code is just an example...the warning is copied from Quartus. In all correctness the warning to match example should have been

    Warning (10665): Bidirectional port "in.mem_A[0][0]" at If.sv(#) has a one-way connection to bidirectional port "out.b1[0][0]"
    Warning (10665): Bidirectional port "in.mem_A[0][1]" at If.sv(#) has a one-way connection to bidirectional port "out.b1[0][1]"
    Warning (10665): Bidirectional port "in.mem_A[0][2]" at If.sv(#) has a one-way connection to bidirectional port "out.b1[0][2]"

  4. #4
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    Default Re: SystemVerilog logic type as bidir

    Hi,
    Quote Originally Posted by click_er View Post
    interface typeA();
    logic[3:0][3:0] mem_A;
    endinterface


    interface typeB();
    logic[3:0] b1;
    logic[3:0] b2;
    logic[3:0] b3;
    endinterface

    module dut(typeA in, typeB out);
    assign out.b1[0] = in.mem_A[0];
    assign out.b2[1] = in.mem_A[1];
    assign out.b3[2] = in.mem_A[2];
    endmodule.
    Don`t you think that, here you are trying to access one interface members by another interface since an interface is a bundle of nets or variables & interface construct in system verilog was specifically created to encapsulate the communication between blocks or modules.
    Refer the attached pdf. for detail about an interface.

    Best Regards
    Vikas Jathar
    (This message was posted on behalf of Intel Corporation)
    Attached Files Attached Files

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