Results 1 to 5 of 5

Thread: Max10 Jtag pins as Differential I/O.

  1. #1
    Join Date
    Jun 2018
    Posts
    3
    Rep Power
    1

    Default Max10 Jtag pins as Differential I/O.

    Good day.
    I've got a problem with jtag pin sharing. My device is Max10 10M08. I use jtag pin sharing option and jtag pins as differential inputs. But when I try to program device with sof file using USB blaster, it fail. When this pins are outputs(not diff), programming is OK. When they are inputs (not diff) it fail too.

    The JTAGEN pin is pulled-up with 10 kOm resistor to 3.3 V.

    So the question is, how to program device using jtag and then use TDO, TMS, TDI and TCK pins as differential inputs?

  2. #2
    Join Date
    Nov 2017
    Posts
    529
    Rep Power
    1

    Default Re: Max10 Jtag pins as Differential I/O.

    Hi,

    JTAG pins cannot perform as JTAG pins in user mode if you assign any of the JTAG pins as a differential I/O pin.
    You must use the JTAG pins as dedicated pins and not as a user I/O pins during JTAG programming.
    The JTAGEN pin is pulled-up with 10 kOm resistor to 3.3 V.
    Means JTAG pin is used as a dedicated pin.
    Refer https://www.altera.com/en_US/pdfs/li...g_m10_gpio.pdf

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)
    Last edited by Anand Raj Shankar; June 10th, 2018 at 04:39 PM.

  3. #3
    Join Date
    Jun 2018
    Posts
    3
    Rep Power
    1

    Default Re: Max10 Jtag pins as Differential I/O.

    Thank you for your answer.
    I think that if use jtag pin sharing and pulling-up jtagen, you can program fpga via jtag, and after programming pull-down jtagen and use Jtag pins as diff io (after making them diff in pin planner). As I understand it works only with single ended io. But how can I use jtag pins as diff io? In pin planner I see that Jtag pins can be differential.

  4. #4
    Join Date
    Nov 2017
    Posts
    529
    Rep Power
    1

    Default Re: Max10 Jtag pins as Differential I/O.

    Hi AMKozha,
    I think that if use jtag pin sharing and pulling-up jtagen, you can program fpga via jtag
    Yes, You have said the configuration for Dedicated JTAG pins.
    after programming pull-down jtagen and use Jtag pins as diff io (after making them diff in pin planner)
    Not possible.
    If you intend to switch back and forth between user I/O pins and JTAG pin functions using the JTAGEN pin, all JTAG pins must be assigned as single-ended I/O pins or
    voltage-referenced I/O pins. Schmitt trigger input is the recommended input buffer.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)
    Last edited by Anand Raj Shankar; June 12th, 2018 at 12:20 AM.

  5. #5
    Join Date
    Jun 2018
    Posts
    3
    Rep Power
    1

    Default Re: Max10 Jtag pins as Differential I/O.

    Quote Originally Posted by Anand Raj Shankar View Post

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)
    Thanks for your explanation. It's help me to understand why it doesn't work. But my question about using jtag pins as diff io has no answer. Is it possible somehow?

    May be using of internal configuration with pof file or two configuration images?

Similar Threads

  1. Can not simulate MAX10 with Differential IO buffers (quartus prime)
    By swinchen in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 2
    Last Post: January 31st, 2018, 09:08 AM
  2. Unused Differential I/O pins & External memory interface pins
    By Thulasi11106 in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 1
    Last Post: November 6th, 2013, 07:21 AM
  3. How can I get the signal from differential I/O pins
    By TianEnjoy in forum General Altera Discussion
    Replies: 2
    Last Post: November 3rd, 2011, 02:11 PM
  4. Assigning LVDS (differential) pins
    By jasper4 in forum Quartus II and EDA Tools Discussion
    Replies: 6
    Last Post: February 23rd, 2011, 08:44 PM
  5. Differential pins and clock constraints
    By gorski123 in forum Quartus II and EDA Tools Discussion
    Replies: 1
    Last Post: January 20th, 2011, 10:20 AM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •