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Thread: Vhdl

  1. #1
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    Default Vhdl

    I need help with the following task in the VHDL program: Based on the DE2 development board, design a 4-bit Johnson counter. The meter's status is to be displayed on 4 7-segment LED displays (eg 1110). The change in the meter's status is taking place run automatically, e.g. every 1s. Develop a test environment for the designed system.

    I need to combine these two codes into one? 4-bit Johnson counter:
    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    
    entity Ring_counter is
    Port( CLOCK: in STD_LOGIC;
    RESET: in STD_LOGIC;
    Q: out STD_LOGIC_VECTOR( 3 downto 0 ) );
    end Ring_counter;
    
    architecture Behavioral of Ring_counter is
    signal q_tmp: std_logic_vector( 3 downto 0 ):= "0001";
    begin
    process( CLOCK, RESET )
    begin
    if RESET = '1' then
    q_tmp <= "0001";
    elsif Rising_edge( CLOCK ) then
         q_tmp( 1 ) <= q_tmp( 0 );
    
    q_tmp( 2 ) <= q_tmp( 1 );
    q_tmp( 3 ) <= q_tmp( 2 );
    q_tmp( 0 ) <= q_tmp( 3 );
    end if;
    end process;
    Q <= q_tmp;
    end Behavioral;

  2. #2
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    Default Re: Vhdl

    Operate the 4 segment display 7

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    entity lcd_dek is port(
    din: in std_logic_vector( 3 downto 0 );
    clk: in std_logic;
    bp: inout std_logic;
    segm_o: out std_logic_vector( 6 downto 0 )
    );
    end lcd_dek;
    architecture ar_dyn of lcd_dek is
    signal segm: std_logic_vector( 6 downto 0 );
    begin
    with din select
    --gfedcba
    segm <= "0111111" when "0000", -- 0
    "0000110" when "0001", -- 1
    "1011011" when "0010", -- 2
    "1001111" when "0011", -- 3
    "1100110" when "0100", -- 4
    "1101101" when "0101", -- 5
    "1111101" when "0110", -- 6
    "0000111" when "0111", -- 7
    "1111111" when "1000", -- 8
    "1101111" when "1001", -- 9
    "0000000" when others; --
    wygaszenie
    segm_o( 0 ) <= segm( 0 ) xor bp;
    segm_o( 1 ) <= segm( 1 ) xor bp;
    segm_o( 2 ) <= segm( 2 ) xor bp;
    segm_o( 3 ) <= segm( 3 ) xor bp;
    segm_o( 4 ) <= segm( 4 ) xor bp;
    segm_o( 5 ) <= segm( 5 ) xor bp;
    segm_o( 6 ) <= segm( 6 ) xor bp;
    bp <= clk;
    end ar_dyn
    I am asking you to check the correctness and help in this task

  3. #3
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    Default Re: Vhdl

    Hi,
    I need to combine these two codes into one? 4-bit Johnson counter:
    1. Either you combine these two entities in one or instantiate the “lcd_dek” entity in “Ring_counter” entity with required signals/variables & component declaration.
    2. Check the DE2 development board crystal frequency & write the vhdl code to step down the frequency up to few Hz then & then only you can observe the display.
    3. Write the test bench & check functionality.
    4. The better way, first try to display simple program like “Hello world” on the DE2 development board.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards
    Vikas Jathar
    (This message was posted on behalf of Intel Corporation)

  4. #4
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    Default Re: Vhdl

    Hello there, this code did not work, so I created a new 4-bit counter and text environment for it but I can not display the signal on 4 7- segment displays ????

    Code:
    architecture beh of johnson_counter is
    signal opt: std_logic_vector( 3 downto 0 );
    begin
    process( clk, rst )
    begin
    if( rst = '1' ) then
         opt <= "0000";
    
    elsif( rising_edge( clk ) ) then
    opt <=( not opt( 0 ) ) & opt( 3 downto 1 );
    end if;
    end process;
    op <= opt;
    end beh;[ / CPP ]
    
    [ code src = "C++" ] library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    
    entity johnson_counter_tb is
    
    end johnson_counter_tb;
    
    architecture Behavioral of johnson_counter_tb is
    
    component johnson_counter is
    port( clk: in std_logic;
    rst: in std_logic;
    op: out std_logic_vector( 3 downto 0 ) );
    
    end component;
    
    signal clk_tb, rst_tb: std_logic:= '1';
    signal op_tb: std_logic_vector( 3 downto 0 );
    constant clk_period: time:= 10 ns;
    
    begin
    
    DUT: johnson_counter port map( clk_tb, rst_tb, op_tb );
    
    clk_process: process
    begin
    clk_tb <= not( clk_tb );
    wait for clk_period / 2;
    end process;
    
    main_process: process
    begin
    wait for 10 ns;
    rst_tb <= '0';
    wait for 100 ns;
    end process;
    end Behavioral;

  5. #5
    Daixiwen is offline Moderator **Forum Master**
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    Default Re: Vhdl

    What is the result of your testbench? What did you expect and what did you get?
    Definition of a man-year: 730 people trying to finish the project before lunch

  6. #6
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    Default Re: Vhdl

    In my task, it's all about making any Jonson counter. Which will be displayed on 4 seven segment LED displays. The status of the display changes every 1s. And develop a text environment.

  7. #7
    Daixiwen is offline Moderator **Forum Master**
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    Default Re: Vhdl

    If I'm not mistaken the last code you provided, if connected to 4 leds, will turn each led on one by one, until all 4 are on, and then turn them off. If you intended to use those signals on the common pins of the 7 segment displays it will not work as expected because you will have often several display activated at the same time. The first code you provided will be better suited for this.
    You have the code to control the common pin, and the code to translate from a binary value to 7 segments. Now you need to implement registers with BCD counters and connect everything together.
    Definition of a man-year: 730 people trying to finish the project before lunch

  8. #8
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    Default Re: Vhdl

    Code:
       
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity Counter2_VHDL is
       port( Clock_enable_B: in std_logic;
     	 Clock: in std_logic;
     	 Reset: in std_logic;
     	 Output: out std_logic_vector(0 to 3));
    end Counter2_VHDL;
     
    architecture Behavioral of Counter2_VHDL is
       signal temp: std_logic_vector(0 to 3);
    begin   process(Clock,Reset)
       begin
          if Reset='1' then
             temp <= "0000";
          elsif(rising_edge(Clock)) then
             if Clock_enable_B='0' then
                if temp="1001" then
                   temp<="0000";
                else
                   temp <= temp + 1;
                end if;
             end if;
          end if;
       end process;
       Output <= temp;
    end Behavioral;

  9. #9
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    Default Re: Vhdl

    Hi,
    Have you resolved the issue which was you facing? What are you trying to do with this code in previous post?

    Best Regards
    Vikas Jathar
    (This message was posted on behalf of Intel Corporation)

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