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Thread: HPS-to-FPGA DMA Interrupt

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    Default HPS-to-FPGA DMA Interrupt

    Hi there,

    I am working with the Cyclone V and my goal is to transfer Data with the HPS-DMA-Controller (DMA330) and receive an "interrupt" in the FPGA on completion.

    The data transfer is already functioning. I configured the DMA-Controller via the DMAengine-API:

    Code:
    tx = dma_dev->device_prep_dma_memcpy(dma_channel, dma_dst_addr, dma_src_addr, SDMA_BUF_SIZE, DMA_PREP_INTERRUPT );
    cookie = dmaengine_submit(tx);
    dma_async_issue_pending(dma_channel);

    However, I do not receive the interrupt in the FPGA.

    I checked the HPS-to-FPGA-interrupt in Qsys. Which gave me 8 Interrupt lines corresponding to 8 DMA-channels in the DMAC.
    One thing that is not clear to me, that the DMAengine-API "offers" me 32 DMA channels while there are only 8 "physical" DMA-channels.
    How can that be?
    Currently I am using the API-channel nr. 7 and expecting the interrupt on the physical channel nr 7.
    I did a full recompile including SPL and U-boot with Buildroot.


    I would like to narrow this down. I guess either
    - there is no interrupt sent ( descriptor/ DMA-Controller not properly configured)
    or
    - it does not reach the FPGA ( I am missing a step where this HPS-to-FPGA Interrupt connections have to be enabled)
    or
    - I am listening on the wrong DMA-channel-interrupt

    Do you have an Idea what is going wrong here or how to proceed?
    Do you know any documentation about the HPS-to-FPGA Interrupts other than the "Cyclone V Hard Processor System
    Technical Reference Manual" ?

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