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Thread: Quartus II Fitter error in connecting the output of IOPLL to refclk of ATX PLL

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    Default Quartus II Fitter error in connecting the output of IOPLL to refclk of ATX PLL

    Hello,

    I am creating a Quartus project to transmit high-speed data using the Arria 10 Transceiver Native PHY. I am supplying the the serial clock (at 1.5GHz) to the tx_serial_clk0 using Arria 10 Transceiver ATX PLL which generates 1.5GHz clock using input 150MHz clock. I am creating this 150Mhz clock using another PLL (Altera IOPLL) that takes the 50MHz FPGA clock as the input. I have attached the qsys design screenshot of the project.

    The compilation of the design is successful. However, the fitter prompts an error which I am not able to understand. The error prompt is:

    Error (11192): Input port "REF_IQCLK[0]" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" cannot connect to PLD port "OUTCLK[0]" of "IOPLL" for atom "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_iopl l_171_zoxksfy:iopll_0|altera_iopll:altera_iopll_i| twentynm_iopll_ip:twentynm_pll|iopll_inst".
    Extra Info (13133): Output port's "OUTCLK[0]" atom name is "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_iopl l_171_zoxksfy:iopll_0|altera_iopll:altera_iopll_i| twentynm_iopll_ip:twentynm_pll|iopll_inst".
    Extra Info (13134): Input port's "REF_IQCLK[0]" atom name is "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_xcvr _atx_pll_a10_171_7s4kdty:xcvr_atx_pll_a10_0|a10_xc vr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_hssi_pma _lc_refclk_select_mux_inst".
    Extra Info (12879): Input port "REF_IQCLK[0]" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" can connect to:
    Extra Info (12880): Port "O_REFCLK_A[0]" of "HSSI_REFCLK_DIVIDER"


    It basically says that I cannot provide the output of the IOPLL to the pll_refclk0 of the ATX PLL. But, the ATX PLL needs reference clock of 150MHz. It does not make sense to me. Please help.

    Thank you
    Attached Files Attached Files
    Last edited by gusFring; June 13th, 2018 at 11:23 AM.

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