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Thread: Verilog Coding

  1. #1
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    Jun 2018
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    Question Verilog Coding

    Hello,

    I'm getting the following error when I'm implementing the below Verilog code.

    [Synth 8-403] loop limit (65536) exceeded

    parameter N=10;
    parameter M=8;
    parameter depth=(1<<N);


    reg [M-1:0]stack_mem[depth-1:0];


    always@(posedge clk)
    begin
    if (rst==1'b1)
    begin
    next_sp=0;
    dataout=0;
    for(i=0;i<(depth-1);i=i+1)
    begin
    stack_mem[i]=0;
    end
    end
    end


    Here "For loop" has to increase only up to 1023 but again why I'm getting loop limit exceeded error?

    Can anyone help me out?

    Thanks in advance.

  2. #2
    Join Date
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    Default Re: Verilog Coding

    Where is i declared? Probably should be declared as an integer;

    Probably like this, with the added text in red:

    Code:
    always@(posedge clk)
        begin : block_name
        integer i;
        if (rst==1'b1)
            begin
            next_sp=0;
            dataout=0;
            for(i=0;i<(depth-1);i=i+1)
                begin
                stack_mem[i]=0;
                end
            end
        end
    Note that by requiring that clearing the whole memory in one clock cycle be done, you will be forcing the implementation of stack_mem[] to be done be an array of clearable registers, and not using a block_ram type of memory structure. Hope that is what you intend.

    Also clk, rst, next_sp, and dataout need to be declared somewhere (maybe you left out some code ... ?)
    Last edited by ak6dn; June 13th, 2018 at 01:50 PM.

  3. #3
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    Default Re: Verilog Coding

    Thanks for your response. It's my mistake.i declared "i" as a single bit.

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