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Thread: Problem with FIR II core

  1. #11
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    Default Re: Problem with FIR II core

    Thank you kaz!

    I'll try to derive 288MHz

    As a separate question.
    Do you think that there is simple solution of what i want with IP Catalog FIR II core in 72MHz domain?

    Thanks
    Dimitar

  2. #12
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    Default Re: Problem with FIR II core

    Quote Originally Posted by dpenev View Post
    Thank you kaz!

    I'll try to derive 288MHz

    As a separate question.
    Do you think that there is simple solution of what i want with IP Catalog FIR II core in 72MHz domain?

    Thanks
    Dimitar
    The short answer is no
    you can use two parallel sections as even odd samples @ 144. You will need four sub-filters, not worth it and has to be done by hand not fir compiler. After all I assume your output may have to be one stream @ 288

  3. #13
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    Default Re: Problem with FIR II core

    I see.

    Actually my output should be passed the same way I get it (4 consecutive samples at once on each 72Mhz tick).
    My current system is using 72MHz clock.

    The odd/even structure you have in mind is something similar as the polyphase filter decomposition from the multi rate theory I guess?
    Last edited by dpenev; July 10th, 2018 at 08:10 AM.

  4. #14
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    Default Re: Problem with FIR II core

    OK Now I have 288MHz clock to my FIR filter but I seems to get issues with it.
    I have verified that filter 'valid' signal is constant 1 and filter output error[1:0] is 2'b00
    Is this a confirmation that the filter manages to do its calculations on time?
    What is to be expected if the clock reaches the filter maximum performance speed?

    Thanks
    Dimitar

  5. #15
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    Default Re: Problem with FIR II core

    Quote Originally Posted by dpenev View Post
    OK Now I have 288MHz clock to my FIR filter but I seems to get issues with it.
    I have verified that filter 'valid' signal is constant 1 and filter output error[1:0] is 2'b00
    Is this a confirmation that the filter manages to do its calculations on time?
    What is to be expected if the clock reaches the filter maximum performance speed?

    Thanks
    Dimitar
    vin should be continuously high (by your input mux). vout will then be continuously high(by filter). It is single rate so both input and output are running on 288Mhz which is your data rate.

    Your question on filter maximum speed implies some uncertainty of your thoughts here. can you explain it further.

  6. #16
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    Default Re: Problem with FIR II core

    OK sorry I was not clear.

    My filter contains 11 coefficients. It is symmetrical FIR.
    I am not sure how this is internally implemented but I guess I have 6 multipliers (because of the symmetry) and some adders.
    I guess multipliers are implemented by a dedicated blocks and probably they all work in parallel?

    Anyways I was wondering what will happen if the period of my clock is shorter compared to the time needed for internal FIR logic to complete the calculations of the current output sample. Will the filter clear the output 'valid' flag in this case?
    I have no idea if with my 288MHz and 11 taps I am close to this point or not? I am using Stratix IV.

    Clarification is very welcome.

  7. #17
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    Default Re: Problem with FIR II core

    Quote Originally Posted by dpenev View Post
    OK sorry I was not clear.

    My filter contains 11 coefficients. It is symmetrical FIR.
    I am not sure how this is internally implemented but I guess I have 6 multipliers (because of the symmetry) and some adders.
    I guess multipliers are implemented by a dedicated blocks and probably they all work in parallel?

    Anyways I was wondering what will happen if the period of my clock is shorter compared to the time needed for internal FIR logic to complete the calculations of the current output sample. Will the filter clear the output 'valid' flag in this case?
    I have no idea if with my 288MHz and 11 taps I am close to this point or not? I am using Stratix IV.

    Clarification is very welcome.
    FPGA -unlike software- can work from full parallism to full serial processing as chosen by designer.
    It may require pipeline delay for timing closure issues i.e. output could be late but then it is fixed initial delay and stream comes out continuous thereafter.

  8. #18
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    Default Re: Problem with FIR II core

    If I have to ask different way.
    What do you think is the maximum clock rate I can clock my 11 taps symmetric FIR from the IP core
    if enough resources on Stratix IV silicon?

  9. #19
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    Default Re: Problem with FIR II core

    Quote Originally Posted by dpenev View Post
    If I have to ask different way.
    What do you think is the maximum clock rate I can clock my 11 taps symmetric FIR from the IP core
    if enough resources on Stratix IV silicon?
    In fpga jargon you are asking for "fmax". That is implementation issue. For a good design you can well get 300MHz in your device

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