AlteraForum.com — TimeQuest Issue with wrong launch clock & wrong latch edge

In my VHDL code, I use rising_edge for shift registers to latch data.

But TimeQuest report timing of these shift registers using falling edge of clock.
What's wrong?

pls see the detailed VHDL code below:
LIBRARY IEEE;
USE IEEE.stdlogic1164.ALL;
USE IEEE.stdlogicunsigned.ALL;
USE IEEE.stdlogicarith.ALL;
entity FreqMeasure_ADReader is

port
(
   IN_AD_SCLK     : in std_logic;
   IN_TARGET_SIGNAL  : in std_logic;
   IN_AD_DATA         : in std_logic;
   OUT_AD_SCLK        : out std_logic;
  OUT_AD_VALUE      : out integer       
);

constant cADRESOLUTION : integer :=16;
end entity;
architecture registeradsclk of FreqMeasureADReader is
component SynSignalGeneratorCrossingClockDomain is
port
(
INCLK : in stdlogic;
INSTROBE : in stdlogic;
OUTSYNSIGNAL : inout std_logic
);
end component;

signal   s_ad_sdata_shift_reg   : std_logic_vector(c_AD_RESOLUTION-1 downto 0);
signal   s_ad_sclk_enable :std_logic;
signal   s_ad_sclk :std_logic;
signal   s_counter :integer range c_AD_RESOLUTION*2 downto 0;
signal   s_target_signal : std_logic;
signal   s_counter_synclear : std_logic;

begin

stargetsignal <= NOT INTARGETSIGNAL;
countersyncleargen: SynSignalGeneratorCrossingClockDomain PORT MAP(INADSCLK, stargetsignal, scountersynclear);
sclkengen: process(INADSCLK, scountersynclear)
begin
if(scountersynclear = '1') then
scounter <= 0;
elsif(risingedge(INADSCLK)) then
if(scounter = 1) then
sadsclkenable <= '0';
scounter <= scounter + 1;
elsif(scounter < cADRESOLUTION * 2) then
sadsclkenable <= '0';
scounter <= scounter + 1;
else
sadsclkenable <= '1';
end if;
end if;
end process;
adsclkgen: process(INADSCLK, sadsclkenable)
begin
if(sadsclkenable = '0') then
if(risingedge(INADSCLK)) then
sadsclk <= NOT sadsclk;
end if;
else
sadsclk <= '1';
end if;
end process;
OUTADSCLK <= sadsclk;
shiftreg0: process(sadsclk)
begin
if(risingedge(sadsclk)) then
sadsdatashiftreg(0) <= INADDATA;
end if;
end process;

shiftreggen: for i in 1 to sadsdatashiftreg'high generate
process(sadsclk)
begin
if(risingedge(sadsclk)) then
sadsdatashiftreg(i) <= sadsdatashiftreg(i-1);
end if; end process;
end generate;
OUTADVALUE <= CONVINTEGER(sadsdatashiftreg);
end registeradsclk;

Pls see the following TimeQuest screen shot pic:
http://blogimg.chinaunix.net/blog/upfile2/080124210233.jpg

And TimeQuest report timing of |FreqMeasure_ADReader:|sadsclk with wrong launch clock, the launch clock should be FreqMeasureNiosII:inst|pll:thepll|altpllpll:thepll|altpll:altpllcomponent|clk2.
Pls note that: *|FreqMeasureADReader:*|sadsclk is a toggle register launch & latch by FreqMeasureNiosII:inst|pll:thepll|altpllpll:thepll|altpll:altpllcomponent|_clk2, which make TimeQuest confused.
How can I correct TimeQuest to report correct timing in this case?
Pls also see the following screen shot pic:
http://blogimg.chinaunix.net/blog/upfile2/080124210633.jpg

TimeQuest Issue with wrong launch clock & wrong latch edge

TimeQuest Issue with wrong launch clock & wrong latch edge ¶